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27 results on '"Ihsen Alouani"'

1. A novel multi-view pedestrian detection database for collaborative Intelligent Transportation Systems

Author

Mohamed Ali Mahjoub, Atika Rivenq, Ihsen Alouani, Anouar Ben Khalifa, Laboratory of Advanced Technology and Intelligent Systems (LATIS), Ecole Nationale d'Ingénieurs de Sousse (ENISo), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Université de Sousse, Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), and Institut National des Sciences Appliquées (INSA)

Subjects
Scheme (programming language), Collaborative intelligence, Computer Networks and Communications, Computer science, Pedestrian detection, 02 engineering and technology, computer.software_genre, Task (project management), [SPI]Engineering Sciences [physics], 11. Sustainability, 0202 electrical engineering, electronic engineering, information engineering, Intelligent transportation system, ComputingMilieux_MISCELLANEOUS, computer.programming_language, Environment perception, Monocular, Database, 020206 networking & telecommunications, Multi-view, Hardware and Architecture, Infrastructure to vehicle, 020201 artificial intelligence & image processing, computer, CNN, Software
Abstract

International audience; Recent advances in machine-learning, especially in deep neural networks have significantly accelerated the development and deployment of transport-oriented intelligent designs with increasingly high efficiency. While these technologies are exceptionally promising toward revolutionizing our current mobility and reducing the number of road accidents, the way to safe Intelligent Transportation Systems (ITS) remains long. Since pedestrians are the most vulnerable road users, designing accurate pedestrian detection methods is a priority task. However, traditional monocular pedestrian detection methods are limited, especially in occlusion handling. Hence, a collaborative perception scheme in which vehicles no longer restrict their input data to their immediate embedded sensors and rather exploit data from remote sensors is necessary to achieve a more comprehensive environment perception. In this work, we propose a novel public dataset: Infrastructure to Vehicle Multi-View Pedestrian Detection Database (I2V-MVPD) that combines synchronized images from both a mobile camera embedded in a car and a static camera in the road infrastructure. We also propose a new multi-view pedestrian detection framework based on collaborative intelligence between vehicles and infrastructure. Our results show a significant improvement in detection performance over monocular detection.

Published
2020

2. Defensive approximation: securing CNNs using approximate computing

Author

Mouna Baklouti, Mohamed Abid, Nael Abu-Ghazaleh, Khaled N. Khasawneh, Amira Guesmi, Tarek Frikha, Ihsen Alouani, Université de Sfax - University of Sfax, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), George Mason University [Fairfax], University of California [Riverside] (UCR), University of California, Partially supported by NSF grants CNS-1646641, CNS-1619322 and CNS-1955650, Université catholique de Lille (UCL)-Université catholique de Lille (UCL), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Université catholique de Lille (UCL)-Université catholique de Lille (UCL)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), University of California [Riverside] (UC Riverside), and University of California (UC)

Subjects
FOS: Computer and information sciences, Computer Science - Machine Learning, Computer Science - Cryptography and Security, Computer systems organization, Network reliability, Computer science, Embedded systems, 0211 other engineering and technologies, 02 engineering and technology, Convolutional neural network, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], Machine Learning (cs.LG), Image (mathematics), [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [SPI]Engineering Sciences [physics], Redundancy, Robustness (computer science), Classifier (linguistics), 0202 electrical engineering, electronic engineering, information engineering, [INFO]Computer Science [cs], 021110 strategic, defence & security studies, business.industry, Embedded and cyber-physical systems, Deep learning, Robotics, Energy consumption, [SPI.TRON]Engineering Sciences [physics]/Electronics, 020202 computer hardware & architecture, Dependable and fault-tolerant systems and networks, Range (mathematics), Noise (video), Artificial intelligence, Networks, business, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, Cryptography and Security (cs.CR), Algorithm, Network properties
Abstract

In the past few years, an increasing number of machine-learning and deep learning structures, such as Convolutional Neural Networks (CNNs), have been applied to solving a wide range of real-life problems. However, these architectures are vulnerable to adversarial attacks. In this paper, we propose for the first time to use hardware-supported approximate computing to improve the robustness of machine learning classifiers. We show that our approximate computing implementation achieves robustness across a wide range of attack scenarios. Specifically, for black-box and grey-box attack scenarios, we show that successful adversarial attacks against the exact classifier have poor transferability to the approximate implementation. Surprisingly, the robustness advantages also apply to white-box attacks where the attacker has access to the internal implementation of the approximate classifier. We explain some of the possible reasons for this robustness through analysis of the internal operation of the approximate implementation. Furthermore, our approximate computing model maintains the same level in terms of classification accuracy, does not require retraining, and reduces resource utilization and energy consumption of the CNN. We conducted extensive experiments on a set of strong adversarial attacks; We empirically show that the proposed implementation increases the robustness of a LeNet-5 and an Alexnet CNNs by up to 99% and 87%, respectively for strong grey-box adversarial attacks along with up to 67% saving in energy consumption due to the simpler nature of the approximate logic. We also show that a white-box attack requires a remarkably higher noise budget to fool the approximate classifier, causing an average of 4db degradation of the PSNR of the input image relative to the images that succeed in fooling the exact classifier, Comment: ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2021)

Published
2021

3. A memory reliability enhancement technique for multi bit upsets

Author

Alexandre Chabot, Smail Niar, Ihsen Alouani, Reda Nouacer, Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA), Université catholique de Lille (UCL)-Université catholique de Lille (UCL), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Université catholique de Lille (UCL)-Université catholique de Lille (UCL)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), and no information

Subjects
Computer science, 02 engineering and technology, Theoretical Computer Science, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [SPI]Engineering Sciences [physics], MBU, Memory, Fault injection, 0202 electrical engineering, electronic engineering, information engineering, Redundancy (engineering), Time overhead, [INFO]Computer Science [cs], Electronic systems, 020206 networking & telecommunications, Reliability, Computing systems, Reliability engineering, [SPI.TRON]Engineering Sciences [physics]/Electronics, Hardware and Architecture, Control and Systems Engineering, Modeling and Simulation, Signal Processing, 020201 artificial intelligence & image processing, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, Information Systems, Voltage
Abstract

International audience; Technological advances allow the production of increasingly complex electronic systems. Nevertheless, technology and voltage scaling increased dramatically the susceptibility of new devices not only to Single Bit Upsets (SBU), but also to Multiple Bit Upsets (MBU). In safety critical applications, it is mandatory to provide fault-tolerant systems, providing high reliability while meeting applications requirements. The problem of reliability is particularly expressed within the memory which represents more than 80 % of systems on chips. To tackle this problem we propose a new memory reliability techniques referred to as DPSR: Double Parity Single Redundancy. DPSR is designed to enhance computing systems resilience to SBU and MBU. Based on a thorough fault injection experiments, DPSR shows promising results; It detects and corrects more than 99.6 % of encountered MBU and has an average time overhead of less than 3 %.

Published
2021

4. An Investigation on Inherent Robustness of Posit Data Representation

Author

Farhad Merchant, Ihsen Alouani, Rainer Leupers, Anouar Ben Khalifa, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), Université catholique de Lille (UCL)-Université catholique de Lille (UCL), COMmunications NUMériques - IEMN (COMNUM - IEMN), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Université catholique de Lille (UCL)-Université catholique de Lille (UCL)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), Laboratory of Advanced Technology and Intelligent Systems (LATIS), Ecole Nationale d'Ingénieurs de Sousse (ENISo), Rheinisch-Westfälische Technische Hochschule Aachen University (RWTH), Integrated Signal Processing Systems, no information, Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), and Rheinisch-Westfälische Technische Hochschule Aachen (RWTH)

Subjects
FOS: Computer and information sciences, 010302 applied physics, Very-large-scale integration, Reliability theory, Computer science, 02 engineering and technology, Fault injection, External Data Representation, Posit Arithmetic, Reliability, 01 natural sciences, Data type, IEEE floating point, 020202 computer hardware & architecture, Machine Learning, [SPI]Engineering Sciences [physics], Computer engineering, Robustness (computer science), Hardware Architecture (cs.AR), 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Computer Arithmetic, Representation (mathematics), Computer Science - Hardware Architecture
Abstract

As the dimensions and operating voltages of computer electronics shrink to cope with consumers' demand for higher performance and lower power consumption, circuit sensitivity to soft errors increases dramatically. Recently, a new data-type is proposed in the literature called posit data type. Posit arithmetic has absolute advantages such as higher numerical accuracy, speed, and simpler hardware design than IEEE 754-2008 technical standard-compliant arithmetic. In this paper, we propose a comparative robustness study between 32-bit posit and 32-bit IEEE 754-2008 compliant representations. At first, we propose a theoretical analysis for IEEE 754 compliant numbers and posit numbers for single bit flip and double bit flips. Then, we conduct exhaustive fault injection experiments that show a considerable inherent resilience in posit format compared to classical IEEE 754 compliant representation. To show a relevant use-case of fault-tolerant applications, we perform experiments on a set of machine-learning applications. In more than 95% of the exhaustive fault injection exploration, posit representation is less impacted by faults than the IEEE 754 compliant floating-point representation. Moreover, in 100% of the tested machine-learning applications, the accuracy of posit-implemented systems is higher than the classical floating-point-based ones., To appear in VLSID 2021

Published
2021

5. Securing Deep Spiking Neural Networks against Adversarial Attacks through Inherent Structural Parameters

Author

Alberto Marchisio, Rida El-Allami, Ihsen Alouani, Muhammad Shafique, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), Université catholique de Lille (UCL)-Université catholique de Lille (UCL), Vienna University of Technology (TU Wien), New York University [Abu Dhabi], NYU System (NYU), COMmunications NUMériques - IEMN (COMNUM - IEMN), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Université catholique de Lille (UCL)-Université catholique de Lille (UCL)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), Intel Corporation, Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA)

Subjects
FOS: Computer and information sciences, Optimization, Computer Science - Machine Learning, Computer science, 02 engineering and technology, [INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE], Machine learning, computer.software_genre, SNN, Machine Learning (cs.LG), Machine Learning, Spiking Neural Networks, [SPI]Engineering Sciences [physics], Adversarial system, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], Deep Learning, [INFO.INFO-LG]Computer Science [cs]/Machine Learning [cs.LG], Robustness (computer science), Neuromorphic, 0202 electrical engineering, electronic engineering, information engineering, Robustness, Adversarial Attacks, Vulnerability (computing), Spiking neural network, business.industry, Deep learning, 020202 computer hardware & architecture, Variable (computer science), Neuromorphic engineering, Parameters, Security, 020201 artificial intelligence & image processing, Artificial intelligence, Noise (video), business, computer, Analysis
Abstract

Deep Learning (DL) algorithms have gained popularity owing to their practical problem-solving capacity. However, they suffer from a serious integrity threat, i.e., their vulnerability to adversarial attacks. In the quest for DL trustworthiness, recent works claimed the inherent robustness of Spiking Neural Networks (SNNs) to these attacks, without considering the variability in their structural spiking parameters. This paper explores the security enhancement of SNNs through internal structural parameters. Specifically, we investigate the SNNs robustness to adversarial attacks with different values of the neuron's firing voltage thresholds and time window boundaries. We thoroughly study SNNs security under different adversarial attacks in the strong white-box setting, with different noise budgets and under variable spiking parameters. Our results show a significant impact of the structural parameters on the SNNs' security, and promising sweet spots can be reached to design trustworthy SNNs with 85% higher robustness than a traditional non-spiking DL system. To the best of our knowledge, this is the first work that investigates the impact of structural parameters on SNNs robustness to adversarial attacks. The proposed contributions and the experimental framework is available online to the community for reproducible research., Accepted for publication at the 24th Design, Automation and Test in Europe (DATE'21), February, 2021

Published
2020

6. A novel public dataset for multimodal multiview and multispectral driver distraction analysis: 3MDAD

Author

Mohamed Ali Mahjoub, Anouar Ben Khalifa, Ihsen Alouani, Imen Jegham, Laboratory of Advanced Technology and Intelligent Systems (LATIS), Ecole Nationale d'Ingénieurs de Sousse (ENISo), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)

Subjects
Computer science, Multispectral, Multispectral image, Advanced driver assistance systems, 02 engineering and technology, Machine learning, computer.software_genre, Task (project management), [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], Multiview, [SPI]Engineering Sciences [physics], [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], Distraction, 0202 electrical engineering, electronic engineering, information engineering, [INFO]Computer Science [cs], Electrical and Electronic Engineering, Intelligent transportation system, Set (psychology), Modalities, Modality (human–computer interaction), business.industry, Driver distraction, 020206 networking & telecommunications, Public dataset, Safe driving, [SPI.TRON]Engineering Sciences [physics]/Electronics, Signal Processing, Multimodal, 020201 artificial intelligence & image processing, Computer Vision and Pattern Recognition, Artificial intelligence, business, computer, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, Software
Abstract

International audience; Driver distraction and fatigue have become one of the leading causes of severe traffic accidents. Hence, driver inattention monitoring systems are crucial. Even with the growing development of advanced driver assistance systems and the introduction of third-level autonomous vehicles, this task is still trending and complex due to challenges such as the illumination change and the dynamic background. To reliably compare and validate driver inattention monitoring methods, a limited number of public datasets are available. In this paper, we put forward a public, well-structured and complete dataset, named Multiview, Multimodal and Multispectral Driver Action Dataset (3MDAD). The dataset is mainly composed of two sets: the first one recorded in daytime and the second one at nighttime. Each set consists of two synchronized data modalities, both from frontal and side views. More than 60 drivers are asked to execute 16 in-vehicle actions under a wide range of naturalistic driving settings. In contrast to other public datasets, 3MDAD presents multiple modalities, spectrums and views under different time and weather conditions. To highlight the utility of our dataset, we independently analyze the driver action recognition results adapted to each modality and those obtained of several combinations of modalities.

Published
2020

7. Deep CNN-based Pedestrian Detection for Intelligent Infrastructure

Author

Bilel Tarchoun, Anouar Ben Khalifa, Mohamed Ali Mahjoub, Imen Jegham, Ihsen Alouani, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), and Institut National des Sciences Appliquées (INSA)

Subjects
Computer science, Pedestrian detection, Real-time computing, Advanced driver assistance systems, 02 engineering and technology, Pedestrian, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], Task (project management), Databases, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [SPI]Engineering Sciences [physics], 0202 electrical engineering, electronic engineering, information engineering, Training, [INFO]Computer Science [cs], Intelligent transportation system, Lighting, Detector, Intelligent decision support system, Detectors, 020206 networking & telecommunications, Cameras, [SPI.TRON]Engineering Sciences [physics]/Electronics, Task analysis, Feature extraction, 020201 artificial intelligence & image processing, Transfer of learning, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing
Abstract

ISBN 978-1-7281-7514-0 ; e-ISBN 978-1-7281-7513-3; International audience; Autonomous driving systems and driver assistance systems are becoming the center of attention in transport technology. Given its safety criticality, pedestrian detection is a highly important task. Transport oriented intelligent systems use embedded sensors for the detection task. However, vehicle side detection is starting to show its limitations especially when dealing with certain challenges such as occlusions. In this paper, we propose an infrastructure side perception system that has a bird's eye view. We introduce a new deep pedestrian detector that can use the detection results to warn nearby vehicles of the presence of pedestrians on the road. The results show that our proposed system is able to detect pedestrians in most conditions with 70.41% precision and 69.17% recall.

Published
2020

8. Neuroattack: undermining spiking neural networks security through externally triggered bit-flips

Author

Alberto Marchisio, Valerio Venceslai, Maurizio Martina, Muhammad Shafique, Ihsen Alouani, Vienna University of Technology (TU Wien), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Politecnico di Torino = Polytechnic of Turin (Polito), This work has been partially supported by the Doctoral CollegeResilient Embedded Systems which is run jointly by TU Wien’sFaculty of Informatics and FH-Technikum Wien., Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), and Institut National des Sciences Appliquées (INSA)

Subjects
FOS: Computer and information sciences, Computer Science - Machine Learning, Computer Science - Cryptography and Security, Computer science, Distributed computing, Reliability (computer networking), Machine Learning (stat.ML), 02 engineering and technology, 01 natural sciences, SNN, Machine Learning (cs.LG), [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], Machine Learning, Spiking Neural Networks, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [SPI]Engineering Sciences [physics], Hardware, Statistics - Machine Learning, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, [INFO]Computer Science [cs], Fault-Injection Attacks, Resilience (network), Adversarial Attacks, 010302 applied physics, Spiking neural network, Deep Neural Networks, Resilience, Machine Learning, Spiking Neural Networks, Reliability, Adversarial Attacks, Fault-Injection Attacks, Deep Neural Networks, DNN, SNN, Security, Resilience, Cross-Layer, Biological system modeling, Reliability, 020202 computer hardware & architecture, [SPI.TRON]Engineering Sciences [physics]/Electronics, Cross layer, Cross-Layer, Security, Noise (video), Biological neural networks, Cryptography and Security (cs.CR), [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, DNN
Abstract

Due to their proven efficiency, machine-learning systems are deployed in a wide range of complex real-life problems. More specifically, Spiking Neural Networks (SNNs) emerged as a promising solution to the accuracy, resource-utilization, and energy-efficiency challenges in machine-learning systems. While these systems are going mainstream, they have inherent security and reliability issues. In this paper, we propose NeuroAttack, a cross-layer attack that threatens the SNNs integrity by exploiting low-level reliability issues through a high-level attack. Particularly, we trigger a fault-injection based sneaky hardware backdoor through a carefully crafted adversarial input noise. Our results on Deep Neural Networks (DNNs) and SNNs show a serious integrity threat to state-of-the art machine-learning techniques., Accepted for publication at the 2020 International Joint Conference on Neural Networks (IJCNN)

Published
2020

9. Are CNNs reliable enough for critical applications? An exploratory study

Author

Mohamed Ayoub Neggaz, Fadi J. Kurdahi, Ihsen Alouani, Smail Niar, Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA), Centro de Estudios Científicos (CECs), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)

Subjects
Computer science, Reliability (computer networking), Feature extraction, Exploratory research, 02 engineering and technology, Multiple Event Upsets, Machine learning, computer.software_genre, Convolutional neural network, Reliability engineering, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], Machine Learning, [SPI]Engineering Sciences [physics], [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], 0202 electrical engineering, electronic engineering, information engineering, [INFO]Computer Science [cs], Engines, Electrical and Electronic Engineering, Implementation, Quantization (signal), Fault tolerant systems, business.industry, Convolutional Neural Networks, Reliability, 020202 computer hardware & architecture, [SPI.TRON]Engineering Sciences [physics]/Electronics, Hardware and Architecture, Artificial intelligence, business, Embedded Systems, computer, Single Event Upsets, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, Software
Abstract

International audience; Resource-constrained CNN implementations are subject to various reliability threats. This article provides an exploratory study investigating the impact of faults (soft errors modeled as bit flips) across the parameters of CNNs and the impact on the CNN weights, which can be used to create reliability-aware design guidelines. -Theocharis Theocharides, University of Cyprus -Muhammad Shafique, Technische Universitat Wien

Published
2020

10. OLIMP: A Heterogeneous Multimodal Dataset for Advanced Environment Perception

Author

Atika Menhaj, Yassin El Hillali, Ihsen Alouani, Amira Mimouna, Anouar Ben Khalifa, Abdeldjalil Ouahabi, Abdelmalik Taleb-Ahmed, Najoua Essoukri Ben Amara, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)

Subjects
multi-modality, fusion, Computer Networks and Communications, Computer science, media_common.quotation_subject, lcsh:TK7800-8360, Context (language use), 02 engineering and technology, 01 natural sciences, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], law.invention, Task (project management), [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [SPI]Engineering Sciences [physics], Human–computer interaction, law, Perception, 11. Sustainability, 0202 electrical engineering, electronic engineering, information engineering, [INFO]Computer Science [cs], Electrical and Electronic Engineering, Radar, Intelligent transportation system, media_common, business.industry, Deep learning, 010401 analytical chemistry, lcsh:Electronics, intelligent transportation systems, object detection, Object detection, [SPI.TRON]Engineering Sciences [physics]/Electronics, 0104 chemical sciences, public dataset, Hardware and Architecture, Control and Systems Engineering, Signal Processing, 020201 artificial intelligence & image processing, Artificial intelligence, business, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing
Abstract

International audience; A reliable environment perception is a crucial task for autonomous driving, especially in dense traffic areas. Recent improvements and breakthroughs in scene understanding for intelligent transportation systems are mainly based on deep learning and the fusion of different modalities. In this context, we introduce OLIMP: A heterOgeneous Multimodal Dataset for Advanced EnvIronMent Perception. This is the first public, multimodal and synchronized dataset that includes UWB radar data, acoustic data, narrow-band radar data and images. OLIMP comprises 407 scenes and 47,354 synchronized frames, presenting four categories: pedestrian, cyclist, car and tram. The dataset includes various challenges related to dense urban traffic such as cluttered environment and different weather conditions. To demonstrate the usefulness of the introduced dataset, we propose a fusion framework that combines the four modalities for multi object detection. The obtained results are promising and spur for future research.

Published
2020
Full Text
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11. Cross-layer CNN approximations for hardware implementation

Author

Hamza Ouarnoughi, Karim M. A. Ali, Ihsen Alouani, Smail Niar, Abdessamad Ait El Cadi, Rincón, Fernando, Barba, Jesús, So, Hayden K. H., Diniz, Pedro, Caba, Julián, Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), and Institut National des Sciences Appliquées (INSA)

Subjects
Computer science, 02 engineering and technology, 010501 environmental sciences, 01 natural sciences, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], Convolution, Reduction (complexity), [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [SPI]Engineering Sciences [physics], 0202 electrical engineering, electronic engineering, information engineering, [INFO]Computer Science [cs], Pruning (decision trees), Field-programmable gate array, Quantization (image processing), ComputingMilieux_MISCELLANEOUS, FPGA, 0105 earth and related environmental sciences, Artificial neural network, business.industry, 020208 electrical & electronic engineering, CNNs, Approximate computing, Object detection, [SPI.TRON]Engineering Sciences [physics]/Electronics, business, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, Computer hardware, MNIST database
Abstract

Oral Session 7 - Design Space Exploration & Estimation TechniquesISBN 978-3-030-44533-1 ; e-ISBN 978-3-030-44534-8; International audience; Convolution Neural Networks (CNNs) are widely used for image classification and object detection applications. The deployment of these architectures in embedded applications is a great challenge. This challenge arises from CNNs’ high computation complexity that is required to be implemented on platforms with limited hardware resources like FPGA. Since these applications are inherently error-resilient, approximate computing (AC) offers an interesting trade-off between resource utilization and accuracy. In this paper, we study the impact on CNN performances when several approximation techniques are applied simultaneously. We focus on two of the widely used approximation techniques, namely quantization and pruning. Our experimental results showed that for CNN networks of different parameter sizes and 3% loss in accuracy, we can obtain up to 27.9%–47.2% reduction in computation complexity in terms of FLOPs for CIFAR-10 and MNIST datasets.

Published
2020

12. Power-efficient reliable register file for aggressive-environment applications

Author

Ozcan Ozturk, Ihsen Alouani, Smail Niar, Hamzeh Ahangari, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA), Bilkent University [Ankara], Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Ahangari, Hamzeh, and Öztürk, Özcan

Subjects
normal operating conditions, Computer science, reduced power budget, power aware computing, microprocessor chips, floating point critical bits, Register file, 02 engineering and technology, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [SPI]Engineering Sciences [physics], [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], serious design challenge, embedded system manufacturers, 0202 electrical engineering, electronic engineering, information engineering, flip-flops, RF architecture, Data processing, adjacent byte-level narrow-width values, highly aggressive operating conditions, counterpart register, integrated circuit reliability, on-board data processing, fault immune computing systems, 020202 computer hardware & architecture, Significand, Hardware and Architecture, aggressive environments, Instruction pipeline, embedded systems, low power budget, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, Computer hardware, Floating point, Exploit, floating point RF reliability enhancement techniques, Power budget, processor pipeline, aggressive-environment applications, critical element, adjacent register hardened RF, integer registers, nonutilised bits, [INFO]Computer Science [cs], Electrical and Electronic Engineering, reliability, business.industry, Power efficient, [SPI.TRON]Engineering Sciences [physics]/Electronics, floating point arithmetic, authors propose, embedded processors, power-efficient reliable register file, error hardening, business, Software
Abstract

International audience; In a context of increasing demands for on-board data processing, insuring reliability under reduced power budget is a serious design challenge for embedded system manufacturers. Particularly, embedded processors in aggressive environments need to be designed with error hardening as a primary goal, not an afterthought. As Register File (RF) is a critical element within the processor pipeline, enhancing RF reliability is mandatory to design fault immune computing systems. This study proposes integer and floating point RF reliability enhancement techniques. Specifically, the authors propose Adjacent Register Hardened RF, a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening integer registers at runtime. Registers are paired together by special switches referred to as joiners and non-utilised bits of each register are exploited to enhance the reliability of its counterpart register. Moreover, they suggest sacrificing the least significant bits of the Mantissa to enhance the reliability of the floating point critical bits, namely, Exponent and Sign bits. The authors' results show that with a low power budget compared to state of the art techniques, they achieve better results under both normal and highly aggressive operating conditions.

Published
2020

13. Vision-based human action recognition: an overview and real world challenges

Author

Imen Jegham, Ihsen Alouani, Mohamed Ali Mahjoub, Anouar Ben Khalifa, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), and Institut National des Sciences Appliquées (INSA)

Subjects
Computer science, 02 engineering and technology, Large range, Action recognition, Motion (physics), Field (computer science), [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], Pathology and Forensic Medicine, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [SPI]Engineering Sciences [physics], Application domain, 0202 electrical engineering, electronic engineering, information engineering, Datasets, [INFO]Computer Science [cs], Vision based, 020206 networking & telecommunications, Data science, [SPI.TRON]Engineering Sciences [physics]/Electronics, Computer Science Applications, Bad weather, Medical Laboratory Technology, Activity recognition, Real world challenges, 020201 artificial intelligence & image processing, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, Law, Vision-based, Information Systems
Abstract

International audience; Within a large range of applications in computer vision, Human Action Recognition has become one of the most attractive research fields. Ambiguities in recognizing actions does not only come from the difficulty to define the motion of body parts, but also from many other challenges related to real world problems such as camera motion, dynamic background, and bad weather conditions. There has been little research work in the real world conditions of human action recognition systems, which encourages us to seriously search in this application domain. Although a plethora of robust approaches have been introduced in the literature, they are still insufficient to fully cover the challenges. To quantitatively and qualitatively compare the performance of these methods, public datasets that present various actions under several conditions and constraints are recorded. In this paper, we investigate an overview of the existing methods according to the kind of issue they address. Moreover, we present a comparison of the existing datasets introduced for the human action recognition field.

Published
2020

14. CNTFET design of a multiple-port ternary register file

Author

Lobna A. Said, Ihsen Alouani, Ahmed G. Radwan, Amr Mohammaden, Mohammed E. Fouda, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA), Université catholique de Lille (UCL)-Université catholique de Lille (UCL), COMmunications NUMériques - IEMN (COMNUM - IEMN), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), and Université catholique de Lille (UCL)-Université catholique de Lille (UCL)-Centrale Lille-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-JUNIA (JUNIA)

Subjects
Computer science, Dynamic, Register file, Binary number, 02 engineering and technology, Ternary computer, CNTFET, 01 natural sciences, law.invention, [SPI]Engineering Sciences [physics], law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Flip flop, Hardware_ARITHMETICANDLOGICSTRUCTURES, Ternary logic gates, 010302 applied physics, Hardware_MEMORYSTRUCTURES, 020208 electrical & electronic engineering, General Engineering, Information processing, CNTEFT, Carbon nanotube field-effect transistor, Latch, D-latch, CMOS, Ternary operation, Realization (systems), Hardware_LOGICDESIGN
Abstract

International audience; Ternary number system offers higher information processing within the same number of digits when compared to binary systems. Such advantage motivated the development of ternary processing units especially with CNTFET which offers better power and delay results compared to CMOS-based realization. In this paper, we propose a variety of circuit realizations for the ternary memory elements that are needed in any processor including ternary D-latch, and ternary D-flip-flop. These basic building blocks are then used to design a ternary register file with multiple read and write ports. This paper is an attempt to investigate the performance aspects of using ternary RF to open the gate of more contributions and research in the direction of full ternary computer architecture. The proposed designs have been compared in terms of power, area, and latency at different supply voltages and operating temperatures.

Published
2021

15. HEAP

Author

Atika Rivenq, Amira Guesmi, Mouna Baklouti, Mohamed Abid, Ihsen Alouani, Tarek Frikha, École Nationale d'Ingénieurs de Sfax | National School of Engineers of Sfax (ENIS), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA), and NONE FOUND.

Subjects
Floating point, Design space exploration, Computer science, Single Precision, 02 engineering and technology, 01 natural sciences, Power budget, Single-precision floating-point format, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [SPI]Engineering Sciences [physics], [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, [INFO]Computer Science [cs], Approximate Computing, Heap (data structure), 010302 applied physics, Genetic Algorithm, low power, Energy consumption, Design Space Exploration, [SPI.TRON]Engineering Sciences [physics]/Electronics, 020202 computer hardware & architecture, Computer engineering, Systems design, Floating Point Multiplication, Multiplier (economics), [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing
Abstract

Session 2 - Security, verification and reliability; International audience; Floating point arithmetic is one of the most commonly used units in nowadays computing systems and is deployed for a wide range of domains and applications. While floating point operators offer high precision calculations, a plethora of applications such as multimedia processing and machine learning tolerate errors and computation imprecision. In a context of limited power budget embedded systems, saving resources and energy with an acceptable precision loss is a challenging design task. Approximate computing is an emerging systems design paradigm that offers promising balance between accuracy on the one hand and power consumption and resource utilization on the other hand. While state of the art approximate techniques offer a wide design space at the operator level, few are the works that consider exploring different techniques to build a heterogeneous comprehensive approximate design. In this paper, we propose HEAP: a heterogeneous approximate floating point multiplier. Based on a design space exploration process, we present an approximation at the transistor level that reduces energy consumption of up to 68%. Experimental study on a set of machine learning applications shows promising results with comparable accuracy to exact multiplier based systems. © 2019 Association for Computing Machinery.

Published
2019

16. MDAD: a multimodal and multiview in-vehicle driver action dataset

Author

Ihsen Alouani, Imen Jegham, Anouar Ben Khalifa, Mohamed Ali Mahjoub, Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), and Institut National des Sciences Appliquées (INSA)

Subjects
Computer science, 02 engineering and technology, Machine learning, computer.software_genre, 01 natural sciences, Field (computer science), [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], Distraction, 0202 electrical engineering, electronic engineering, information engineering, Distracted driving, [INFO]Computer Science [cs], ComputingMilieux_MISCELLANEOUS, Modality (human–computer interaction), Modalities, business.industry, 010401 analytical chemistry, Testbed, 0104 chemical sciences, [SPI.TRON]Engineering Sciences [physics]/Electronics, Action (philosophy), RGB color model, 020201 artificial intelligence & image processing, Artificial intelligence, business, computer, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing
Abstract

“Driver’s distraction is deadly!”. Due to its crucial role in saving lives, driver action recognition is an important and trending topic in the field of computer vision. However, a very limited number of public datasets are available to validate proposed methods. This paper introduces a new public, well structured and extensive dataset, named Multiview and multimodal in-vehicle Driver Action Dataset (MDAD). MDAD consists of two temporally synchronised data modalities from side and frontal views. These modalities include RGB and depth data from different Kinect cameras. Many subjects with various body sizes, gender and ages are asked to perform 16 in-vehicle actions in several weather conditions. Each subject drives the vehicle on multiple trip routes in Sousse, Tunisia, at different times to describe a large range of head rotations, changes in lighting conditions and some occlusions. Our recorded dataset provides researchers with a testbed to develop new algorithms across multiple modalities and views under different illumination conditions. To demonstrate the utility of our dataset, we analyze driver action recognition results from each modality and every view independently, and then we combine modalities and views. This public dataset is of benefit to research activities for humans driver action analysis.

Published
2019

17. A new memory reliability technique for multiple bit upsets mitigation

Author

Alexandre Chabot, Reda Nouacer, Ihsen Alouani, Smail Niar, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA), Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), and Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Computer science, 02 engineering and technology, 01 natural sciences, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [SPI.TRON]Engineering Sciences [physics]/Electronics, 020202 computer hardware & architecture, Reliability engineering, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [SPI]Engineering Sciences [physics], visual_art, 0103 physical sciences, Electronic component, 0202 electrical engineering, electronic engineering, information engineering, Redundancy (engineering), visual_art.visual_art_medium, [INFO]Computer Science [cs], Static random-access memory
Abstract

International audience; Technological advances make it possible to produce increasingly complex electronic components. Nevertheless, these advances are convoyed by an increasing sensitivity to operating conditions and an accelerated aging process. In safety critical applications, it is vital to provide solutions to avoid these limitations and to guarantee a high level of reliability. In most of the existing methods in the literature only Single Event Upsets (SEU) are assumed. The next generations of embedded systems must on one side support Multiple-Bit Upsets (MBU) and avoid to induce a significant memory and processing overheads on the other side. This paper proposes a new method to increase the reliability of SRAM, without dramatically increasing costs in memory space and processing time. Our method, named DPSR for Double Parity Single Redundancy, offers a high level of reliability and takes into fault patterns occurring in real conditions

Published
2019

18. Safe Driving : Driver Action Recognition using SURF Keypoints

Author

Imen Jegham, Ihsen Alouani, Mohamed Ali Mahjoub, Anouar Ben Khalifa, Laboratory of Advanced Technology and Intelligent Systems (LATIS), Ecole Nationale d'Ingénieurs de Sousse (ENISo), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Institut National des Sciences Appliquées (INSA), and NONE FOUND.

Subjects
Safe driving, Computer science, "Safety", "Face", Advanced driver assistance systems, 02 engineering and technology, "Lighting", Computer security, computer.software_genre, 01 natural sciences, [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI], [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], [SPI]Engineering Sciences [physics], "Roads", Distraction, 0202 electrical engineering, electronic engineering, information engineering, Distracted driving, [INFO]Computer Science [cs], Road traffic, 010401 analytical chemistry, Frame (networking), "Vehicles", [SPI.TRON]Engineering Sciences [physics]/Electronics, 0104 chemical sciences, Key (cryptography), "Microelectronics", Action recognition, 020201 artificial intelligence & image processing, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, computer, "Wheels"
Abstract

International audience; Driver distraction is one of the main factors of fatal road traffic injuries. According to the national Highway Traffic Safety Administration (NHTSA), in USA, 3450 are killed by distracted driving, in 2016. In order to save lives, Advanced Driver Assistance Systems (ADAS), more specifically those systems for distracted driver action recognition are introduced. Our method aim to extract, from each frame, a region of interest (KOI) that contains body parts performing in-vehicle actions. These regions hold the most important key points after eliminating those common ones that are similar to the key points of the safe driving actions. The proposed approach was evaluated on the distracted driver detection dataset. Experimental results illustrate the performance of the proposed approach.

Published
2018

19. A Comprehensive Fault Injection Strategy for Embedded Systems Reliability Assessment

Author

Reda Nouacer, Alexandre Chabot, Ihsen Alouani, Smail Niar, Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Centre National de la Recherche Scientifique (CNRS)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Laboratoire MeASI - CEA LIST (MEASI), Département Ingénierie Logiciels et Systèmes (DILS), Laboratoire d'Intégration des Systèmes et des Technologies (LIST), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Paris-Saclay-Laboratoire d'Intégration des Systèmes et des Technologies (LIST), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Paris-Saclay, Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Centre National de la Recherche Scientifique (CNRS), Laboratoire Modélisation et Analyse de Systèmes en Interaction (LMeASI), Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), and Institut National des Sciences Appliquées (INSA)

Subjects
Computer science, Embedded systems, Libraries, Context (language use), 02 engineering and technology, Software reliability, Hardware, Mathematical model, 0202 electrical engineering, electronic engineering, information engineering, [INFO]Computer Science [cs], Reliability (statistics), business.industry, 05 social sciences, 050301 education, Fault injection, Software quality, 020202 computer hardware & architecture, Task (computing), Embedded system, visual_art, New product development, Electronic component, visual_art.visual_art_medium, business, 0503 education, Voltage
Abstract

International audience; The embedded systems industry is moving towards the integration of higher performance, yet less reliable electronic components into new product generations. Technology and voltage scaling increased dramatically the susceptibility of new devices not only to Single Bit Upsets (SBU), but also to Multiple Bit Upsets (MBU). However, the system reliability assessment at the design phase of fault-tolerant computer systems is a complex and critical task. In this context, it is mandatory to enhance reliability analysis and evaluation techniques at early-stage of the system development. In this paper, we present a technique for reliability evaluation of embedded systems at early-stage by taking into account the application behavior and SBU/MBU phenomena. Instead of using the random fault injection, our approach models the architecture behavior under real working conditions. Our results demonstrate the efficiency of the proposed fault injection simulation platform for early-stage reliability studies.

Published
2018

20. A Novel Heterogeneous Approximate Multiplier for Low Power and High Performance

Author

Hamzeh Ahangari, Smail Niar, Ozcan Ozturk, Ihsen Alouani, Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Centre National de la Recherche Scientifique (CNRS)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Ahangari, Hamzeh, and Öztürk, Özcan

Subjects
Adder, General Computer Science, Design space exploration, Computer science, 02 engineering and technology, Transistors, Bottleneck, Parallel multipliers, Space explorations, 0202 electrical engineering, electronic engineering, information engineering, [INFO]Computer Science [cs], Computer architecture, Digital design techniques, Multiplying circuits, Delays, Design parameters, Design paradigm, Electronic circuit, Space exploration, 020208 electrical & electronic engineering, Dissipation, Approximate computing, 020202 computer hardware & architecture, Energy efficiency, Computer engineering, Control and Systems Engineering, Space research, Improving performance, Multiplier (economics), Adders, Efficient energy use
Abstract

International audience; Approximate computing is a design paradigm considered for a range of applications that can tolerate some loss of accuracy. In fact, the bottleneck in conventional digital design techniques can be eliminated to achieve higher performance and energy efficiency by compromising accuracy. In this letter, a new architecture that engages accuracy as a design parameter is presented, where an approximate parallel multiplier using heterogeneous blocks is implemented. Based on design space exploration, we demonstrate that introducing diverse building blocks to implement the multiplier rather than cloning one building block achieves higher precision results. We show experimental results in terms of precision, delay, and power dissipation as metrics and compare with three previous approximate designs. Our results show that the proposed heterogeneous multiplier achieves more precise outputs than the tested circuits while improving performance and power tradeoffs.

Published
2018

21. A Reliability Study on CNNs for Critical Embedded Systems

Author

Pablo R. Lorenzo, Mohamed Ayoub Neggaz, Smail Niar, Ihsen Alouani, INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Centre National de la Recherche Scientifique (CNRS)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC), Institut National des Sciences Appliquées (INSA), Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Centre National de la Recherche Scientifique (CNRS), and NONE FOUND.

Subjects
Computer science, Reliability (computer networking), Embedded systems, Context (language use), 02 engineering and technology, 01 natural sciences, Convolutional neural network, Transient analysis, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Transient (computer programming), [INFO]Computer Science [cs], Sensitivity (control systems), 010302 applied physics, business.industry, Deep learning, Circuit faults, Fault tolerance, Computational modeling, Reliability, 020202 computer hardware & architecture, Variety (cybernetics), Computer engineering, Integrated circuit modeling, Feature extraction, Artificial intelligence, business
Abstract

International audience; Deep learning systems such as Convolutional Neural Networks (CNNs) have shown remarkable efficiency in dealing with a variety of complex real life problems. To accelerate the execution of these heavy algorithms, a plethora of software implementations and hardware accelerators have been proposed. In a context of shrinking devices dimensions, reliability issues of CNN-hosting systems are under-explored. In this paper, we experimentally evaluate the inherent fault tolerance of CNNs by injecting errors within network modules, namely processing elements and memories. Our experiments demonstrate a non uniform sensitivity between different parts of the system. While CNNs are relatively resilient to errors occurring in processing elements, transient faults hitting memories lead to catastrophic degradation of accuracy.

Published
2018
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22. Adaptive Reliability for Fault Tolerant Multicore Systems

Author

Thomas Wild, Andreas Herkersdorf, Ihsen Alouani, Smail Niar, Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Centre National de la Recherche Scientifique (CNRS)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Technical University of Munich (TUM), and Technische Universität Munchen - Université Technique de Munich [Munich, Allemagne] (TUM)

Subjects
010302 applied physics, Multi-core processor, business.industry, Computer science, Error mitigation, Multiprocessing, Fault tolerance, 02 engineering and technology, 01 natural sciences, Reliability engineering, 020202 computer hardware & architecture, Multicore processing, Degradation, Redundancy, Recovery method, Runtime, Embedded system, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Multicore systems, Redundancy (engineering), Dependability, [INFO]Computer Science [cs], business
Abstract

International audience; In an era of continuously shrinking technology and escalating power density, Multiprocessor System on Chips (MPSoCs) suffer from a growing prominence of device defects and increase of dependability-related issues. This paper tackles the dependability challenge by suggesting an adaptive reliability enhancement strategy for multicore systems. We dynamically adapt the reliability enhancement to the actual tasks requirements as well as cores runtime operating conditions. As reliability improvement may adversely affect the parameters of embedded systems, we suggest a runtime recovery method. In fact, we implement a 3-mode mapping technique to limit redundancy overheads through judicious task migrating and dropping. Our experiments show promising results in terms of error mitigation with controllable power and thermal overheads.

Published
2017

23. Reconfigurable Hardened Latch and Flip-Flop for FPGAs

Author

Hamzeh Ahangari, Smail Niar, Ozcan Ozturk, Ihsen Alouani, Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), and Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Centre National de la Recherche Scientifique (CNRS)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)

Subjects
Triple modular redundancy, Engineering, Logic block, Field programmable gate arrays (FPGA), 02 engineering and technology, Single event upsets, Hardware_PERFORMANCEANDRELIABILITY, VLSI circuits, 01 natural sciences, law.invention, MBus, law, 0202 electrical engineering, electronic engineering, information engineering, Reconfigurability, Hardware_ARITHMETICANDLOGICSTRUCTURES, FPGA, Computer control systems, Flip-flop, Sstatic latch, Integrated circuit reliability, Economic and social effects, Three orders of magnitude, Reconfigurable structure, Latches, Reliability, Reconfigurable computing, Reconfigurable hardware, 020202 computer hardware & architecture, Single event upset, Static latch, Transistors, 0103 physical sciences, Radiation hardening (electronics), Multiple bit upset, [INFO]Computer Science [cs], Field-programmable gate array, 010308 nuclear & particles physics, business.industry, SRAM cells, Field programmable gate arrays, Radiation hardening, Fault tolerant computer systems, Reconfigurable devices, Embedded system, Hardening, business, Hardware_LOGICDESIGN
Abstract

Conference name: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017 Date of Conference: 3-5 July 2017 In this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel reconfigurable structures which bring the reconfigurability of reliability to user latches and flip-flops (FFs) in reconfigurable devices such as FPGAs. Specifically, we implement two reconfigurable storage elements that exploit a trade-off between reliability and amount of available resources. In fault prone conditions, JLatch (or JFF) is configured in such a way that four pre-selected normal static latches (or FFs) are combined together at circuit level to form one hardened storage cell. Solution focuses on transient faults such as soft errors, where we show that critical charge is increased by at least three orders of magnitude (1000X) to practically bring immunity against any Single Event Upset (SEU). If four latches inside an FPGA logic block are far enough, it can effectively cope with Multiple Bit Upsets (MBUs) as well. Additionally, provided that special transistor sizing is applied (only necessary for some latch structures), JLatch and JFF take advantage of a novel self-correcting technique to correct any single fault immediately. Our solution provides reconfigurability of reliability with negligible performance and area overhead with only one (two) extra transistor(s) per latch (FF). The delay of this technique is less than the delay of conventional TMR (Triple Modular Redundancy) technique with a majority voter at output. © 2017 IEEE.

Published
2017

24. AS8‐static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement

Author

Smail Niar, Ahmed M. Eltawil, Fadi J. Kurdahi, Wael M. Elsharkasy, Ihsen Alouani, Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), and Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Centre National de la Recherche Scientifique (CNRS)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)

Subjects
010302 applied physics, Engineering, Hardware_MEMORYSTRUCTURES, business.industry, CPU cache, 02 engineering and technology, Integrated circuit, 01 natural sciences, 020202 computer hardware & architecture, law.invention, Soft error, Control and Systems Engineering, Memory cell, law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, [INFO]Computer Science [cs], Static random-access memory, Electrical and Electronic Engineering, business, Scaling, Random access, Voltage
Abstract

International audience; Soft errors in semiconductor memories occur due to charged particle strikes on sensitive nodes. Technology and voltage scaling increased dramatically the susceptibility of static random access memories (SRAMs) to soft errors. In this study, the authors present AS8-SRAM, a new asymmetric memory cell that enhances the soft error resilience of SRAMs by increasing the cells critical charge. They run Simulation Program with Integrated Circuit Emphasissimulations and system level experiments to validate the AS8-SRAM cell characteristics at circuit level and evaluate the energy and reliability effectiveness of an AS8-SRAM-based cache memory. The authors’ results show that AS8-SRAM presents up to 58 times less failures in time compared to six-transistor SRAM. Moreover, based on embedded benchmarks experimentations, AS8-SRAM achieves up to 22% reduction in energy-delay product without any considerable loss in performance.

Published
2017

25. NS-SRAM: neighborhood solidarity SRAM for reliability enhancement of SRAM memories

Author

Ozcan Ozturk, Hamzeh Ahangari, Ihsen Alouani, and Smail Niar

Subjects
Computer science, Digital storage, Reliability (computer networking), Soft errors, Cache memory, Errors, Static noise margin, Computer control, Systems analysis, 02 engineering and technology, Parallel computing, Read static noise margin (RSNM), Static random access storage, SNM, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Overhead (computing), Static random-access memory, Soft error, Static random access memory, Error correction, Hardware_MEMORYSTRUCTURES, Technology shift, Reliability enhancement, 020208 electrical & electronic engineering, Radiation hardening, Voltage scaling, Reliability, SRAM, 020202 computer hardware & architecture, Soft error rate, Bit error rate, Cache, Random errors, Error resilience, Random access, Random access storage, Voltage
Abstract

Date of Conference: 31 Aug.-2 Sept. 2016 Conference name: 2016 Euromicro Conference on Digital System Design (DSD) Technology shift and voltage scaling increased the susceptibility of Static Random Access Memories (SRAMs) to errors dramatically. In this paper, we present NS-SRAM, for Neighborhood Solidarity SRAM, a new technique to enhance error resilience of SRAMs by exploiting the adjacent memory bit data. Bit cells of a memory line are paired together in circuit level to mutually increase the static noise margin and critical charge of a cell. Unlike existing techniques, NS-SRAM aims to enhance both Bit Error Rate (BER) and Soft Error rate (SER) at the same time. Due to auto-adaptive joiners, each of the adjacent cells' nodes is connected to its counterpart in the neighbor bit. NS-SRAM enhances read-stability by increasing critical Read Static Noise Margin (RSNM), thereby decreasing faults when circuit operates under voltage scaling. It also increases hold-stability and critical charge to mitigate soft-errors. By the proposed technique, reliability of SRAM based structures such as cache memories and register files can drastically be improved with comparable area overhead to existing hardening techniques. Moreover it does not require any extra-memory, does not impact the memory effective size, and has no negative impact on performance. © 2016 IEEE.

Published
2016

26. Register file reliability enhancement through adjacent narrow-width exploitation

Author

Ozcan Ozturk, Hamzeh Ahangari, Ihsen Alouani, Atika Rivenq, Smail Niar, Universite Bilkent [Ankara], Bilkent University [Ankara], Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), COMmunications NUMériques - IEMN (COMNUM - IEMN), Institut d’Électronique, de Microélectronique et de Nanotechnologie - Département Opto-Acousto-Électronique - UMR 8520 (IEMN-DOAE), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Centre National de la Recherche Scientifique (CNRS)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)-Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), and Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Centre National de la Recherche Scientifique (CNRS)

Subjects
Fault-tolerant architectures, Exploit, 7T/14T SRAM, Computer science, Narrow-width, Register file, 02 engineering and technology, "Radio frequency", [SPI]Engineering Sciences [physics], Radio frequency, "Microprocessors", 0202 electrical engineering, electronic engineering, information engineering, Nanotechnology, [INFO]Computer Science [cs], Computer architecture, Microprocessors, Radiation hardening, Electronic circuit, Integrated circuit reliability, Bit cell, "Computer architecture", Narrow width, business.industry, Reliability enhancement, SRAM cells, 020208 electrical & electronic engineering, "SRAM cells", Fault tolerance, Integrated control, Reliability, 020202 computer hardware & architecture, Soft error rate, Soft error, CMOS, SER, Embedded system, RF reliability, "Integrated circuit reliability", Critical elements, Hardening, Processor pipelines, "Registers", business, Register files
Abstract

Date of Conference: 12-14 April 2016 Conference name: 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS) Due to the increasing vulnerability of CMOS circuits, new generations of microprocessors require an inevitable focus on reliability issues. As the Register File (RF) constitutes a critical element within the processor pipeline, it is mandatory to enhance the RF reliability to develop fault tolerant architectures. This paper proposes Adjacent Register Hardened RF (ARH), a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening registers at runtime. Registers are paired together by some special switches referred to as joiners. Dummy sign bits of each register are used to keep redundant data of its counterpart register. We use 7T/14T SRAM cell [6] to combine redundant bits together to make a single bit cell which is, by far, more resilient against faults. Our simulations show that with 3% to 12% power overhead and 10% to 20% increase in area, in comparison to baseline RF, we can obtain up to 80% reduction in soft error rate (SER). © 2016 IEEE.

Published
2016

27. ARABICA: A Reconfigurable Arithmetic Block for ISA Customization

Author

Mazen A. R. Saghir, Ihsen Alouani, Smail Niar, Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Centre National de la Recherche Scientifique (CNRS)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France), Electrical & Computer Engineering Program, and Texas A&M University at Qatar

Subjects
Interconnection, Cycles per instruction, Computer science, 02 engineering and technology, Personalization, Instruction set, Embedded applications, Computer architecture, 020204 information systems, 0202 electrical engineering, electronic engineering, information engineering, Range (statistics), [INFO]Computer Science [cs], Hardware_ARITHMETICANDLOGICSTRUCTURES, Architecture, Arithmetic, ComputingMilieux_MISCELLANEOUS, Block (data storage)
Abstract

We propose a dynamically reconfigurable arithmetic block architecture for customizing embedded application processor instruction sets. Our architecture uses medium-grained arithmetic blocks and a dedicated but reconfigurable interconnection network to support a wide range of instruction-set extensions. Our experimental results demonstrate the performance of our arithmetic block compared to a general-purpose processor, and its area- and energy-efficiency compared to dedicated arithmetic circuits.

Published
2014

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