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Background: In patients with critically ill COVID-19 pneumonia, alveoli or small airways are filled with a large amount of highly viscous exudates or mucus, leading to airway occlusion. This is currently a difficult point in mechanical ventilation treatment of these patients. The estimation of airway opening pressures and effective mucus clearance are therefore two issues that clinicians are most concerned about. Methods: We retrospectively analyzed respiratory data from 24 critical ill patients with confirmed COVID-19 who received invasive mechanical ventilation and recruitment maneuver at Jinyintan Hospital in Wuhan, China, and found the extraordinarily high inspiratory plateau pressures. A computational model of airway opening was subsequently introduced to investigate possible fluid dynamic mechanisms. Using various types of fluids as lower airway secretions simulants, we further predicted airway opening pressures and suction pressures in critically ill patients with COVID-19. Findings: Among 24 critically ill patients in this retrospective study, the inspiratory plateau pressures ranged from 45 cmH2O to 60 cmH2O, and the mean was 52.4±4.4 cmH2O (mean±[SD]). Patients had low static compliance (23.1±7.3 ml/cmH2O), high alveolar dead space fraction (45±9 percent of tidal volume). Particularly, the capnograms presented a spike-like appearance with an upward slope during the expiratory plateau, indicting the existence of airway obstruction. Our simulation results showed that properties of airway secretions affected the airway opening pressures and suction pressures. When secretions simulants had viscosity similar to that of medicinal glycerin at room temperature or presented rheological properties like peanut butter, the airway opening pressures could be as high as 40~50 cmH2O; the negative pressure needed for secretions suctioning could exceed 20 kPa, likely causing the closures of the distal airways. Interpretation: In a proportion of critically ill patients with COVID-19, limiting plateau pressure to 30 cmH2O may not guarantee the opening of airways due to the presence of highly viscous lower airway secretions, not to mention spontaneous inspiratory efforts. Active airway humidification and effective expectorant drugs are therefore strongly recommended during airway management. Funding Statement: This work was supported by the National Natural Science Foundation of China (81971807, 11532003, 31670950) and Special Project of the National Natural Science Foundation of China (82041003). Declaration of Interests: The authors declare no competing interests. Ethics Approval Statement: The Ethics Committee of Jinyintan Hospital approved the study (KY-2020-56.01). Written informed consent was waived due to the retrospective manner of this study.

In this study, a method for optimizing a weighted nuclear norm model is proposed. This model optimization solution employs a soft-thresholding operation on the singular values of an observation matrix. To determine the soft-thresholding, we focused on the unique properties of a class of special matrices, termed rank-order similar matrices (ROSMs). The threshold determination problem was solved during training by exploiting these properties. In addition, we applied this optimization method to image denoising. In this application, the denoising does not work on the whole image at once, but rather relies on a set of ROSMs. Each matrix in the set is an ROSM, built by stacking non-local similar patch vectors. This optimization method is applied to every ROSM in the set to obtain estimates of the underlying patches, which are aggregated to reconstruct a restored image. Simulation results of 154 noisy images indicate that the proposed optimization method achieves the same peak signal to noise ratio/mean structural similarity index measure results as those achieved by several other state-of-the-art methods such as block-matching and 3D filtering and weighted nuclear norm minimization. It also outperforms many state-of-the-art methods such as nuclear norm minimization, in terms of the visual quality of images.

The trifluoroacetate metal-organic deposition (TFA-MOD) is one of the most appealing routes for the growth of high-quality YBa2Cu3O7-δ (YBCO) coated conductors (CCs) due to its advantages of low cost and high efficiency. However, the puzzle of the inhomogeneities in microstructures and superconducting properties of YBCO CCs prepared based on the TFA-MOD route remain still a challenge. In this paper, 10 cm long YBCO films were prepared under different low-pressure conditions. These YBCO films were deposited on buffered Hastelloy C276 tapes using a dip coater. The effect of different ambient pressures on the microstructure and critical current density of YBCO films was investigated. High critical current density (JC) YBCO coated conductors with good homogeneity were obtained. The JC values (77 K, self-field) at different positions along the length direction of YBCO coated conductor were around 3.5–4 MA/cm2. The results showed that only under a suitable pressure the homogeneities of the microstructure and critical current density along the length direction of coated conductor can be greatly improved. The improvement was mainly ascribed to good texture and the absence of impurity phases BaF2 and Ba4Y2O7 in the films.

3-D convolutional neural networks (3-D CNNs) are used efficiently in many computer vision applications. Most previous work in this area has concentrated only on design and optimization of accelerators for 2-D CNNs, with few attempts having been made to accelerate 3-D CNNs on FPGA. We find the acceleration of 3-D CNNs on FPGA to be challenging due to their high computational complexity and storage demands. More importantly, although the computational patterns of 2-D and 3-D CNNs are analogous, the conventional approaches that have been adopted for acceleration of 2-D CNNs may be unfit for 3-D CNN acceleration. In this paper, in order to accelerate 2-D and 3-D CNNs using a uniform framework, we first propose a uniform template-based architecture that uses templates based on the Winograd algorithm to ensure the rapid development of 2-D and 3-D CNN accelerators. Then, with the aim of efficiently mapping all layers of 2-D /3-D CNNs onto a pipelined accelerator, techniques are developed to improve the throughput and computational efficiency of the accelerator, including layer fusion, layer clustering, and workload-balancing scheme. Finally, we demonstrate the effectiveness of the deep pipelined architecture by accelerating real-life 2-D and 3-D CNNs on the state-of-the-art FPGA platform. On VCU118, we achieve 3.7 TOPS for VGG-16, which outperforms state-of-the-art FPGA-based CNN accelerators. Comparisons with CPU and GPU solutions demonstrate that our implementation of 3-D CNN achieves gains of up to $17.8\times $ and $64.2\times $ in performance and energy relative to a CPU solution, and a $5.0\times $ energy efficiency gain over a GPU solution.

This paper presents a framework for converting P4 programs to VHDL and then implementing them on Field-Programmable Gate Array (FPGA) platforms. In this framework, a match-action-based hardware architecture is introduced with clearly designed components, which correspond to the described functionalities in the P4 programs. A pre-built template library is used for the compilation that includes optimized VHDL templates corresponding to specific clearly designed components. From the output of a standard frontend P4 compiler, the proposed compiler extracts parameters and relationships within the functions being employed, maps them to corresponding templates by calling, configuring, optimizing and instantiating them, and finally generates the appropriate FPGA code. A pre-built evaluation library is also proposed that helps the compiler to optimize the implementation during the mapping phase. A prototype of this framework is also implemented and evaluated; in this process, it is found that the generated processors use few resources and have high throughput and low latency. Compared with a state-of-the-art solution, the packet processing time is halved. In addition, the generated processors are able to operate at a line rate of nearly 100 Gigabits per second for a basic layer-3 forwarding application.

Deep learning (DL) has been widely adopted in various domains of artificial intelligence (AI), achieving dramatic developments in industry and academia. Besides giant AI companies, numerous small and medium-sized enterprises, institutes, and universities (EIUs) have focused on the research and development (R&D) of DL. Considering the high cost of datacenters and high performance computing (HPC) systems, EIUs prefer adopting off-the-shelf GPU clusters as a DL R&D platform for multiple users and developers to process diverse DL workloads. In such scenarios, the scheduling of multiple DL tasks on a shared GPU cluster is both significant and challenging in terms of efficiently utilizing limited resources. Existing schedulers cannot predict the resource requirements of diverse DL workloads, leading to the under-utilization of computing resources and a decline in user satisfaction. This paper proposes GENIE, a QoS-aware dynamic scheduling framework for a shared GPU cluster, which achieves users’ QoS guarantee and high system utilization. In accordance with an exhaustive characterization, GENIE analyzes the key factors that affect the performance of DL tasks and proposes a prediction model derived from lightweight profiling to estimate the processing rate and response latency for diverse DL workloads. Based on the prediction models, we propose a QoS-aware scheduling algorithm to identify the best placements for DL tasks and schedule them on the shared cluster. Experiments on a GPU cluster and large-scale simulations demonstrate that GENIE achieves a QoS-guarantee percentage improvement of up to 67.4 percent and a makespan reduction of up to 28.2 percent, compared to other baseline schedulers.

Copper slag is a by-product waste during copper pyrometallurgy. The piling-stack of copper slag not only occupies a large quantity of plowland, but causes potential danger for local residents. In order to reduce the storage of copper slag, this study prepared concretes by replacing ordinary cement by copper slag. The mechanical properties, phase composition, micrographs, pozzolanic activity and volume stability of the compound cementitious materials were evaluated with fly ash as control. It was found that when the content of copper slag was 5%-10%, the best mechanical properties of concretes were obtained. The phase composition of hydration products of copper slag and fly ash based cementitious materials was almost identical. The micrographs and pozzolanic activity showed that copper slag had stronger reactivity than fly ash. Copper slag based pastes had good volume stability. Copper slag presented a potential application in mortars and concretes.

In this paper, double images encrypted method in the 4f system of image subtraction/addition is proposed. Encryption and decryption are implemented in the same system of image subtraction/addition while the encryption and decryption of two images are once addition and subtraction process of images respectively which will improve the feasibility of implementation in actual optics. So this method has high practicality and utilization ratio with high information processing speed. Furthermore, system parameters of the configuration can also serve as additional keys for encryption and the two images are mutual keys, so the security performance of the encryption system is also improved. Numerical simulation results demonstrate the feasibility and flexibility of the proposed method.

Network telemetry is vital to various network applications, including network anomaly detection, capacity planning, and congestion alleviation. State-of-the-art network telemetry systems are claimed to be scalable, flexible, all-purpose, and accurate. They adopt interval approaches that track network traffic in each interval and collect statistics for analysis at a specific epoch. However, interval methods are impaired by collecting inconsistency and clearing inconsistency, which pollute statistics. Moreover, The state-of-the-art centralized controllers have long latency, which aggravates the discrepancy. Accordingly, we propose the interleaved sketch, a consistent and decentralized network telemetry system across all switches. Each switch has two asymmetric sketches that work in an interleaved fashion, and is self-supervised to improve consistency. The distributed control plane extracts the flow characteristics and provides network-wide telemetry with low latency. We build a P4 prototype of our proposed interleaved sketch and test it on a Barefoot Tofino switch. Experimental results demonstrate that our interleaved sketch achieves ideal accuracy at line speed, with 6% resource overhead.

FT-Matrix is a typical vector-SIMD architecture that refines the cooperation between scalar and vector units. This approach is widely used in digital signal processing, high-performance computing, and artificial intelligence, among other fields. FT-Matrix currently adopts C vector extension as the main programming model, improving the utilization efficiency of SIMD by providing explicit vector extension API. Moreover, it is difficult to efficiently transplant parallel programs (OpenCL, CUDA) adopted by users. This paper proposes an automatic mapping and code optimization method for OpenCL kernels on FT-Matrix architecture. The proposed approach solves these challenges by means of work item coalescing, slicing and rotation, and instruction-level code optimization. Preliminary results show that our method can achieve high performance and good hardware utilization for OpenCL kernels, as well as decreasing the programming difficulty on FT-Matrix.

Ubiquitous computation, which promoted by Rapid development of Wireless Sensor Network (WSN) technologies cuts across many areas of modern day living, Internet of Things has been identified as one of Network Infrastructure in the next generation of application domains. An architecture based on cloud computing at the center, which contribute to highly flexibility and scalablity, is an extensively used scheme to construct IOT applications. With growing number of intelligent terminals and third part application accessing on the platform, the Qos problem caused by the large-scale concurrent access rise to the surface. To address this question, a self-adaption Multi-level Feedback Queue Scheduling policy, used to reduce mean turnaround time and complexity of scheduling, based on Recurrent Neural Network (RNN) is presented in this paper. Feature parameters of queues and tasks are used as input of network, the calculated parameters are exported to optimize queue parameters continuously. This research implement a prototype of this scheme. According To demonstrate the efficiency, this thesis give performance results from our prototype and other scheduling policy.

Per-flow traffic measurement has emerged as a critical but challenging task in data centers in recent years in the face of massive network traffic. Many approximate methods have been proposed to resolve the existing resource-accuracy trade-off in per-flow traffic measurement, one of which is the sketch-based method. However, sketches are affected by their high computational cost and low throughput, moreover, their measurement accuracy is hard to guarantee under the conditions of changing network bandwidth or flow size distribution. Recently, FPGAplatforms have been widely deployed in data centers, as they demonstrate a good fit for high-speed network processing. In this work, we aim to address the problem of per-flow traffic measurement from a hardware architecture perspective. We thus design SAPTM, a pipelined systolic array-like architecture for high-throughput per-flow traffic measurement on FPGA. We adopt memory-friendly D-left hashing in the design of SAPTM, which guarantees high space utilization during flow insertion and eviction, successfully addressing the challenge of tracking a high-speed data stream under limited memory resources on FPGA. Evaluations on the Xilinx VCU118 platform with real-world benchmarks demonstrate that SAPTM possesses high space utilization. Comparisons with state-of-the-art sketch-based solutions show that SAPTM outperforms comparison methods in terms of throughput by a factor of 14.1x&ndash, 70.5x without any accuracy loss.

The emergence of programmable switches has boosted lots of research around many network aspects: mea-surements, security, quality of services. To explore the ad-vantages of programmable data planes while preserving the legacy networking systems, deploying programmable switches incrementally may be a more practical solution. In this paper, we deal with the programmable switch deploy problem for sketch-based network measurement, which has been overlooked before. We first analyze the desired properties of a good deployment for sketch-based network measurement with some examples. Based on summarized lessons, we then develop two Integer Linear Programming (ILP) models, namely TraceILP and TopoILP, to solve the deployment problem. If historical traffic traces are provided, TraceILP generates better deployment with historical information. Even if no traces are provided, TopoILP can still make a reasonable strategy according to the network topology. Evaluations on real ISP and datacenter topologies show that pro-posed models guarantee a promising measurement performance with only about 40% devices upgraded to programmable ones.

The sketch structure is widely applied in the network measurement field due to its limited memory usage and simple operation. However, When the less memory space the system occupied, the accuracy decreases. However, as the flow rate rapidly increases, the on-chip memory will become a system bottleneck. HybridSketch provides a methods to save memory and maintain the accuracy of the measurement system. We apply analysis and new algorithms to make it more efficient. We analyze the error bound of the system and observed that the sketch part of the system will lose the precision of the information along with less memory inevitably. So we propose the data augmentation algorithm based on our analysis. We apply it and propose the optimized HybridSketch. We evaluate the performance and present a comparison with the origin algorithm. The results show that optimized HybridSketch provides an 80% precision rate compared to the original one which occupied 10\( \times \) the memory size.

StaaS (Storage as a Service) has been envisioned as the next generation architecture of IT enterprise. Enterprise, individual end users move more and more important information to outsourced data centers, where the data may be misappropriated in the malicious model. Moreover, users hesitate to store data in the cloud storage because of network fluctuation. Security and availability become the main concern of cloud storage. This paper, to address these issues, presents an architecture of High Available cloud Storage Gateway(HASG). In our design, data file is divided into implicit, redundant blocks by file fragment algorithm. Part of these blocks, which are stored on different designated cloud servers, can be used to reconstruct original file. Additionally, dynamic service provider selection algorithm and redundant block mechanism for file updating is proposed to effectuate cost and bandwidth savings and accelerate data accessing. Experimental results illustrates that our design enhanced security of cloud storage and improved data access efficiency.

4,4′,5,5′-tetraacetamine-3,3′-bi(1,2,4-triazole) (TAcABTz) has been synthesized and characterized by X-ray diffraction, FT-IR and 1H and 13C NMR spectroscopy. TAcABTz Ethanol crystallizes in the monoclinic space group P21/n, and x-ray result shows that two triazole rings are almost coplanar except the methyl group. Thermal behaviors were also studied under the non-isothermal conditions by TG-DTA method, showing that two sharp exothermic peaks during thermal decomposition, and the kinetic parameters including activation energy (Ea) and pre–exponential factor (A) are 144.3 kJ mol−1 and 3.603 × 1012 s−1, respectively. In addition, geometry optimization, binding energy and HOMO–LUMO analysis of TAcABTz and TAcABTz Ethanol are conducted by density functional theory DFT/B3LYP calculation method with 6-311 + G** basis set. DFT calculations results show that the conformer A of TAcABTz Ethanol is more stable than conformer B.

The thermal decomposition behaviors of 2,4,6-Trinitrotoluene (TNT) and 1-methoxy-2,4-dinitro-benzene (DNAN) were studied by using a NETSCH company accelerating rate calorimetry. Hazard indicators such as onset temperature, adiabatic temperature rise, initial self-heat temperature, maximum self-heating rate, and time-to-maximum temperature rise rate have been determined directly. The kinetic parameters, such as the activation energy (E a) and the pre-exponential factor (A) were studied from the measured self-heating rate data by assuming order reaction.

Recently correlation filter based trackers have attracted considerable attention for their high computational efficiency. However, they cannot handle occlusion and scale variation well enough. This paper aims at preventing the tracker from failure in these two situations by integrating the depth information into a correlation filter based tracker. By using RGB-D data, we construct a depth context model to reveal the spatial correlation between the target and its surrounding regions. Furthermore, we adopt a region growing method to make our tracker robust to occlusion and scale variation. Additional optimizations such as a model updating scheme are applied to improve the performance for longer video sequences. Both qualitative and quantitative evaluations on challenging benchmark image sequences demonstrate that the proposed tracker performs favourably against state-of-the-art algorithms.

Thermogravimetric-differential scanning calorimeter and accelerating rate calorimeter (ARC) were performed to study the thermal characteristics and kinetics of energetic 5,5′-bistetrazole-1,1′-diolate (1,1-BTO). The DSC measurements showed one endothermic peak and one exothermic peak with decomposition occurring at 219.1, 227.2, 234.0 and 244.1 °C at different heating rates (2, 4, 8 and 15 °C min−1). The value of critical temperature of thermal explosion (T b) and kinetics parameters was calculated, suggesting that 1,1-BTO is stable below the temperature of 175.36 °C. The thermal behavior under adiabatic condition was studied by ARC, depicting that onset temperature was 176.61 °C and the thermal decomposition ended at 215.93 °C, within the time span of 49.04 min. In addition, the thermo-kinetic parameters such as the activation energy E a and pre-exponential factor A under adiabatic condition were also obtained.

The development of modern networking requires that high-performance network processors be designed quickly and efficiently to support new protocols. As a very important part of the processor, the parser parses the headers of the packets&mdash, this is the precondition for further processing and finally forwarding these packets. This paper presents a framework designed to transform P4 programs to VHDL and to generate parsers on Field Programmable Gate Arrays (FPGAs). The framework includes a pipeline-based hardware architecture and a back-end compiler. The hardware architecture comprises many components with varying functionality, each of which has its own optimized VHDL template. By using the output of a standard frontend P4 compiler, our proposed compiler extracts the parameters and relationships from within the used components, which can then be mapped to corresponding templates by configuring, optimizing, and instantiating them. Finally, these templates are connected to output VHDL code. When a prototype of this framework is implemented and evaluated, the results demonstrate that the throughputs of the generated parsers achieve nearly 320 Gbps at a clock rate of around 300 MHz. Compared with state-of-the-art solutions, our proposed parsers achieve an average of twice the throughput when similar amounts of resources are being used.

Network algorithms are building blocks of network applications. They are inspired by emerging commodity programmable switches and the Programming Protocol-Independent Packet Processors (P4) language. P4 aims to provide target-independent programming neglecting the architecture of underlying infrastructure. However, commodity programmable switches have tight programming restrictions due to limited resources and latency. In addition, manufacturers tailor P4 according to their architecture, putting more restrictions on it. These intrinsic and extrinsic restrictions dilute the goal of P4. This paper proposes P4 high-level programming (P4HLP) framework, a suite of toolchains that simplifies P4 programming. The paper highlights three aspects: (i) E-Domino, a high-level programming language that defines both stateless and stateful processing of data plane in C-style codes, (ii) P4HLPc, a compiler that automatically generates P4 programs from E-Domino programs, which removes the barrier between high-level programming and low-level P4 primitives, (iii) modular programming that organizes programs into reusable modules, to enable fast reconfiguration of commodity switches. Results show that P4HLPc is efficient and robust, thus is suitable for data plane high-level programming. Compared with P4, E-Domino saves at least 5.5&times, codes to express the data plane algorithm. P4HLPc is robust to policy change and topology change. The generated P4 programs achieve line-rate processing.

In-memory database can effectively improve the performance of database-centric applications. However, mainstream application-level caching frameworks, such as Memcached, require developers to specify what to cache while developers can hardly understand all intricate details of the application. In this paper, we propose the smart application-level cache configuration (SACC), an automatic cache configuration approach which decouples the cache logic from the application logic. SACC uses the long short term memory model to decide what to cache and then executes caching operation automatically based on the results of the prediction model with no need of manual specifications. We evaluate SACC with both uniform and skewed workloads. Experimental results demonstrate that SACC can significantly improve the performance of application-level cache system.

Three-dimensional (3D) deconvolution is widely used in many computer vision applications. However, most previous works have only focused on accelerating two-dimensional (2D) deconvolutional neural networks (DCNNs) on Field-Programmable Gate Arrays (FPGAs), while the acceleration of 3D DCNNs has not been well studied in depth as they have higher computational complexity and sparsity than 2D DCNNs. In this paper, we focus on the acceleration of both 2D and 3D sparse DCNNs on FPGAs by proposing efficient schemes for mapping 2D and 3D sparse DCNNs on a uniform architecture. Firstly, a pruning method is used to prune unimportant network connections and increase the sparsity of weights. After being pruned, the number of parameters of DCNNs is reduced significantly without accuracy loss. Secondly, the remaining non-zero weights are encoded in coordinate (COO) format, reducing the memory demands of parameters. Finally, to demonstrate the effectiveness of our work, we implement our accelerator design on the Xilinx VC709 evaluation platform for four real-life 2D and 3D DCNNs. After the first two steps, the storage required of DCNNs is reduced up to 3.9&times, Results show that the performance of our method on the accelerator outperforms that of the our prior work by 2.5&times, to 3.6&times, in latency.

Three-dimensional convolutional neural networks (3D CNNs) have become a promising method in lung nodule segmentation. The high computational complexity and memory requirements of 3D CNNs make it challenging to accelerate 3D CNNs on a single FPGA. In this work, we focus on accelerating the 3D CNN-based lung nodule segmentation on a multi-FPGA platform by proposing an efficient mapping scheme that takes advantage of the massive parallelism provided by the platform, as well as maximizing the computational efficiency of the accelerators. Experimental results show that our system integrating with four Xilinx VCU118 can achieve state-of-the-art performance of 14.5 TOPS, in addition with a 29. 4x performance gain over CPU and 10. 5x more energy efficiency over GPU.CCS Concepts • Computer systems organization $\rightarrow$Special purpose systems.

Today’s cloud-based online services are underpinned by distributed key-value stores (KVSs). Keys and values are distributed across back-end servers in such scale-out systems. One primary real-life performance bottleneck occurs when storage servers suffer from load imbalance under skewed workloads. In this paper, we present KVSwitch, a centralized self-managing load balancer that leverages the power and flexibility of emerging programmable switches. The balance is achieved through dynamically predicting the hot items and creating replication strategies according to KVS loading. To overcome the challenges in realizing KVSwitch given the limitations of the switch hardware, we decompose KVSwitch’s functions and carefully design them for the heterogeneous processors inside the switch. We prototype KVSwitch in a Tofino switch. Experimental results show that our solution can effectively keep the KVS servers balanced even under highly skewed workloads. Furthermore, KVSwitch only replicates 70% of hot items and consumes 9.88% of server memory rather than simply replicating all hot items to each server.

Three-dimensional deconvolution is widely used in many computer vision applications. However, most previous works have only focused on accelerating 2D deconvolutional neural networks (DCNNs) on FPGAs, while the acceleration of 3D DCNNs has not been studied in depth as they have higher computational complexity and sparsity than 2D DCNNs. In this paper, we focus on the acceleration of both 2D and 3D DCNNs on FPGAs by proposing efficient schemes for mapping 2D and 3D DCNNs on a uniform architecture. By implementing our design on the Xilinx VC709 platform for four real-life 2D and 3D DCNNs, we can achieve up to 3.0 TOPS with high hardware efficiency. Comparisons with CPU and GPU solutions demonstrate that we can achieve an improvement of up to 63.3X in throughput relative to a CPU solution and an improvement of up to 8.3X in energy efficiency compared to a GPU solution., 5 pages, conference

Lung nodule segmentation is one of the most significant steps in many Computer Aided Detection (CAD) systems used for lung nodule identification and classification. Three-dimensional convolutional neural networks (3D CNNs) have become a promising method in lung nodule segmentation, as this method can achieve higher detection accuracy than conventional methods. It has been proven that FPGAs can provide the most energy-efficient solution for CNN acceleration. However, the high computational complexity and memory requirements of 3D CNNs make it challenging to accelerate 3D CNNs on a single FPGA, as this will further bottleneck the performance of a 3D CNN-based CAD system. Accordingly, in this work, we focus on accelerating the 3D CNN-based lung nodule segmentation on a multi-FPGA platform by proposing an efficient mapping scheme that takes advantage of the massive parallelism provided by the platform, as well as maximizing the computational efficiency of the accelerators. Experimental results show that our system is able to achieve high computational efficiency and thereby a state-of-the-art performance of 14.5 TOPS at 200 MHz. Comparisons with CPU and GPU solutions demonstrate that our system achieves a 29.4x performance gain over CPU and a 10.5x energy efficiency improvement over GPU.

Ceramic particulate reinforced metal matrix composites is a promising material, but it is difficult to be machined. Pulsed laser processing as a advanced technique is widely used in material processing, but the pulsed laser processing of particulate reinforced metal matrix composites is not sufficiently studied. In this work, scanning ablation of SiC particulate reinforced aluminum metal matrix (SiCp/AA2024) composites was conducted using a nanosecond laser. An innovative jump ablation method was proposed, and the composites processing by jump ablation and common ablation were compared. Both plasma’s and nanosecond laser ablation mechanism’s effects on ablation were analyzed. In contrast to common ablation, jump ablation can effectively increase the ablation depth and rate. At an SOR of 95%, the ablation depth was 39 μm and 99 μm in common and jump ablation respectively, and the increasement was nearly 150%. Meanwhile, The matrix and reinforcement phases on the composites’ ablated surface after jump ablation exhibited relatively independent distribution, while the recast layer was thinner and less oxidized than that produced by common ablation.

The newly proposed correlation filter based trackers can achieve appealing performance despite their great simplicity and superior speed. However, this kind of object trackers is not born with scale and aspect ratio adaptability, thus resulting in suboptimal tracking accuracy. To tackle this problem, this paper integrates the class-agnostic detection proposal method, which is widely adopted in object detection area, into a correlation filter tracker. In the tracker part, optimizations such as feature integration, robust model updating and proposal rejection are applied for efficient integration. As for proposal generation, through integrating and comparing four detection proposal generators along with two baseline methods, the quality of detection proposals is found to have considerable influence on tracking accuracy. Therefore, as the most promising proposal generator, EdgeBoxes is chosen and further enhanced with background suppression. Evaluations are mainly performed on a challenging 50-sequence dataset (OTB50) and its two subsets, 28 sequences with significant scale variation and 14 sequences with obvious aspect ratio change. Among the trackers equipped with different proposal generators, state-of-the-art trackers and existing correlation filter variants, our proposed tracker reports the highest accuracy while running efficiently at an average speed of 20.4 frames per second. Additionally, numerical performance analysis in per-sequence manner and experiment results on VOT2014 dataset are also presented to enable deeper insights into our approach.

Dihydroxylammonium 5,5′-bistetrazole-1,1′-diolate (TKX-50) is a newly synthesized explosive with high detonation performance, low impact sensitivity and low toxicity. Hexanitrohexaazaisowurtzitane (CL-20), especially e-CL-20, is currently the highest energy-density explosive. The research on the TKX-50/e-CL-20 cocrystal can improve the defects of single-compound explosives in their application and greatly expand the application range of TKX-50 and CL-20. Seven TKX-50/e-CL-20 cocrystal models were constructed, and the radial distribution function (RDF), X-ray powder diffraction (XRD) and energy calculation were analyzed based on the equilibrium structures of the cocrystal models by molecular dynamics (MD) simulations. The results indicate that the diffraction peaks of the TKX-50/e-CL-20 cocrystal quite differ from TKX-50's and e-CL-20's and new structure forms, hydrogen bond interactions and van der Waals forces exist in the TKX-50/e-CL-20 cocrystal structure, and the cocrystal model of TKX-50 substituted by e-CL-20 on its [011] facet is easiest to form.

4,4'-Azo-bis(1,2,4-triazolone) (ZTO) based salts from alkaline (Li(+), K(+), Na(+), and Cs(+)), alkaline earth metal salts (Mg(2+), Ca(2+), Sr(2+), and Ba(2+)) and hydrazinium salt were synthesized in a simple, straightforward manner and were characterized by IR and NMR spectroscopy, elemental analysis. The single-crystal X-ray diffraction of seven salts (Na(+), K(+), Cs(+), Mg(2+), Ca(2+), Sr(2+), Ba(2+), and N2H5(+)) are also reported. The X-ray structures show that in the title compounds, the metal atoms are bonded to the nitrogen and oxygen atoms in the bistetrazole ring to form a sandwich structure. In addition, the thermal stabilities of all the title compounds were determined using thermogravimetric-differential thermal analysis (TG-DTA). All these new materials exhibit excellent thermal stability, high density, acceptable detonation properties, and excellent insensitivity to impact (h5060 cm). In particular, the barium, caesium and strontium salts are of great interest as potential high-density insensitive materials.

In this study, homogenous Al alloy and SiC materials and SiCp/AA2024 composites with mean particle diameters of 5 μm and 30 μm were irradiated by a single-pulse nanosecond fiber laser with a 200 ns pulse width and 1064 nm wavelength. Using a laser pulse, regular circular heat-affected zones (HAZ) were formed in the homogenous materials. For the composites, an Al allloy matrix was melted and sputtered, and the SiC particles bulged when irradiated by the laser pulse. According to the measured results, the HAZ increased with the pulse energy density in a logarithmic pattern. Nonlinear fitting results demonstrated that the damage thresholds of the composites and SiC homogenous materials were the lowest and highest, respectively. SiCp/AA2024 composites with different mean particle diameters exhibited similar damage thresholds. The measured etching depths of the SiC particles and Al alloy matrix were smaller than the respective values of the homogenous materials. Thermal simulation results revealed that thermal-mechanical coupling occurred between the SiC particles and Al alloy matrix. The SiC particles in the composite heated more rapidly under a nanosecond laser, and the heat was then transferred to the matrix. Large SiC particles constrained the matrix’s molten pool, which accelerated its gasification but hindered further etching.

In recent years, the rapidly growing use of graphs has sparked parallel graph analytics frameworks for leveraging the massive hardware resources, specifically graphics processing units (GPUs). However, the issues of the unpredictable control flows, memory divergence, and the complexity of programming have restricted high-level GPU graph libraries. In this work, we present HPGA, a high performance parallel graph analytics framework targeting the GPU. HPGA implements an abstraction which maps vertex programs to generalized sparse matrix operations on GPUs for delivering high performance. HPGA incorporates high-performance GPU computing primitives and optimization strategies with a high-level programming model. We evaluate the performance of HPGA for three graph primitives (BFS, SSSP, PageRank) with large-scale datasets. The experimental results show that HPGA matches or even exceeds the performance of MapGraph and nvGRAPH, two state-of-the-art GPU graph libraries.

n the scope of numerous AI enterprises and research institutes, a shared server or cluster, which are based on commodity GPU hardwares, need to process multiple diverse CNN-based tasks simultaneously which are submitted by different developers and researchers. Scheduling and processing multiple CNN-based tasks, including training and batch inference, are a significant challenge in these practical scenarios. Previous studies, which focus on either the latency of a single training task or the throughput of multiple inference tasks, cannot effectively exploit the limited system resources available for diverse CNN-based tasks. This paper, for the first time, focuses on this specific AI Research and Development scenario and conducts an series of explorations on characteration and scheduling for CNN-based tasks. In order to evaluate the qualities of processing and scheduling, we propose a series of comprehensive metrics, including user satisfaction and system efficiency. With the metrics, we characterize diverse CNN behaviors of a few typical CNN models under different application and system configurable factors. Then, a heuristic scheduling algorithm informed by our characterization is explored to better allocate computing resources for the upcoming tasks and to schedule them dynamically on the cluster or server. Compared with two baseline strategies, the results, which are evaluated on multi-GPU platforms, show that our proposed algorithm can improve system efficiency by up to 40% and decrease average response latency by around 38% for multiple CNN-based tasks.

Teaching and training for high-performance computing in our college could not catch up with HPC research level. Thus, it is imperative to promote teaching reform on parallel computing course in our college. Our first parallel programming course is mainly for the first-grade graduate students majoring in CS and related branches with no previous HPC training. The goal is to teach them basic parallel programming methods, parallel thinking and parallel problem solving methodology by coding on a real supercomputer; let the students learn some representative parallel application development issues and some big challenges in HPC by project practice. In this article, we will present our course design objective, principles, practical method and outcome. Particularly, programming practice methodology, project organization, incentive mechanism and assessment methods in project practice will be illustrated. Finally, we present some quantitative findings. According to the feedback, our first parallel programming course achieves the effectiveness on inspiring students' enthusiasm for programming and improving students' abilities for problem solving.

In recent years, the rapid-growing scales of graphs have sparked a lot of parallel graph analysis frameworks to leverage the massive hardware resources on CPUs or GPUs. Existing CPU implementations are time-consuming, while GPU implementations are restricted by the memory space and the complexity of programming. In this paper, we present a high performance hybrid CPU-GPU parallel graph analytics framework with good productivity based on GraphMat. We map vertex programs to generalized sparse matrix vector multiplication on GPUs to deliver high performance, and propose a high-level abstraction for developers to implement various graph algorithms with relatively little efforts. Meanwhile, several optimizations have been adopted for reducing the communication cost and leveraging hardware resources, especially the memory hierarchy. We evaluate the proposed framework on three graph primitives (PageRank, BFS and SSSP) with large-scale graphs. The experimental results show that, our implementation achieves an average speedup of 7.0X than GraphMat on two 6-core Intel Xeon CPUs. It also has the capability to process larger datasets but achieves comparable performance than MapGraph, a state-of-the-art GPU-based framework.

With the increasing demand of big data technology, there has been a growing interest of introducing high performance computing in computer science curriculum. One challenge in helping students understand the nature of efficiency and scalability issues in high performance computing is the lack of opportunities for them to be engaged in large-scale applications that run on supercomputer system architecture. This poster presents a collection of example projects that have been used in a parallel computing course in multiple universities in China, including National University of Defense Technology, Sun Yat-sen University and Hunan University. These projects were adopted from a wide range of scientific computing applications such as CFD, text mining of biomedical literature and so on. The large-scale computing resource for courses is supported by two National Supercomputing Centers, one in Guangzhou and the other in Changsha. The poster describes the background, objective, structure, task, practice process and outcome for each project. It also discusses the impact on student understanding all kinds of key topics and major challenges related to computational efficiency and scalability. Such projects build a positive practical environment to make students indulge in doing all kinds of interesting and helpful trials to validate their assumptions, especially when they have different perspectives or results for one problem. The poster presents our design evaluation rubric to reflect the effectiveness of our practice, as well as the statistics about the students" achievements for the last three semesters.

Three-dimensional convolutional neural networks (3D CNNs) are used efficiently in many computer vision applications. Most previous work in this area has concentrated only on designing and optimizing accelerators for 2D CNN, with few attempts made to accelerate 3D CNN on FPGA. We find accelerating 3D CNNs on FPGA to be challenge due to their high computational complexity and storage demands. More importantly, although the computation patterns of 2D and 3D CNNs are analogous, the conventional approaches adopted for accelerating 2D CNNs may be unfit for 3D CNN acceleration. In this paper, in order to accelerate 2D and 3D CNNs using a uniform framework, we propose a uniform template-based architecture that uses templates based on the Winograd algorithm to ensure fast development of 2D and 3D CNN accelerators. Furthermore, we also develop a uniform analytical model to facilitate efficient design space explorations of 2D and 3D CNN accelerators based on our architecture. Finally, we demonstrate the effectiveness of the template-based architecture by implementing accelerators for real-life 2D and 3D CNNs (VGG16 and C3D) on multiple FPGA platforms. On S2C VUS440, we achieve up to 1.13 TOPS and 1.11 TOPS under low resource utilization for VGG16 and C3D, respectively. End-to-end comparisons with CPU and GPU solutions demonstrate that our implementation of C3D achieves gains of up to 13x and 60x in performance and energy relative to a CPU solution, and a 6.4x energy efficiency gain over a GPU solution.

Large-scale floating-point matrix multiplication is a fundamental kernel in many scientific and engineering applications. Most existing work only focus on accelerating matrix multiplication on FPGA by adopting a linear systolic array. This paper towards the extension of this architecture by proposing a scalable and highly configurable multi-array architecture. In addition, we propose a work-stealing scheme to ensure the equality in the workload partition among multiple linear arrays. Furthermore, an analytical model is developed to determine the optimal design parameters. Experiments on a real-life convolutional neural network (CNN) show that we can obtain the optimal extension of the linear array architecture., Comment: This paper has been accepet by IEEE International Symposium on Circuits and Systems (ISCAS 2018)

The growing use of graph in many fields has sparked a broad interest in developing high-level graph analytics programs. Existing GPU implementations have limited performance with compromising on productivity. HPGraph, our high-performance bulk-synchronous graph analytics framework based on the GPU, provides an abstraction focused on mapping vertex programs to generalized sparse matrix operations on GPU as the backend. HPGraph strikes a balance between performance and productivity by coupling high-performance GPU computing primitives and optimization strategies with a high-level programming model for users to implement various graph algorithms with relatively little effort. We evaluate the performance of HPGraph for four graph primitives (BFS, SSSP, PageRank, and TC). Our experiments show that HPGraph matches or even exceeds the performance of high-performance GPU graph libraries such as MapGraph, nvGraph, and Gunrock. HPGraph also runs significantly faster than advanced CPU graph libraries.

Resonance Raman spectroscopy using 532nm excitation was used to distinguish normal brain tissue from different grades of glioma tissues. Principal component analysis was used to analyze the spectral data and achieved high accuracy.

The solubility of newly insensitive energetic material dihydroxylammonium 5,5′-bis(tetrazole)-1,1′-diolate (TKX-50) was measured in ethyl acetate, ethanol, deionized water, dimethyl fumarate (DMF), formic acid, toluene, and dimethyl sulfoxide (DMSO) between 293.15 and 323.15 K at atmospheric pressure by the gravimetric method, which is increased with an increase of temperature. The order of the solubility is ethyl acetate < ethanol < toluene < deionized water < DMF < formic acid < DMSO. The experimental mole fraction solubility data were correlated with a simple Apleblat equation, showing a good fitting between the experimental data and Apleblat equation.

RISC-V is a new open-source general-purpose instruction set architecture (ISA) developed by the University of California, Berkeley. It allows everyone to design their hardware circuits based on application characteristics and can be used in embedded devices, desktop computer and high-performance servers. In this paper, we use the RISC-V processor to design a fast network packet processing system. It aims to use less power and lower price to provide a faster network data processing capability for upper-layer applications in SDN and NFV. According to the results in our prototype on Field Programmable Gate Array (FPGA), our system has a comparable performance with DPDK, one of the fastest packet processing frameworks on the ×86 platform. It is worth mentioning that our system has higher (about 7.75 times) network packets processing energy efficiency than DPDK.

Convolutional neural networks have proven to be highly successful in applications such as image classification, object tracking, and many other tasks based on 2D inputs. Recently, researchers have started to apply convolutional neural networks to video classification, which constitutes a 3D input and requires far larger amounts of memory and much more computation. FFT based methods can reduce the amount of computation, but this generally comes at the cost of an increased memory requirement. On the other hand, the Winograd Minimal Filtering Algorithm (WMFA) can reduce the number of operations required and thus can speed up the computation, without increasing the required memory. This strategy was shown to be successful for 2D neural networks. We implement the algorithm for 3D convolutional neural networks and apply it to a popular 3D convolutional neural network which is used to classify videos and compare it to cuDNN. For our highly optimized implementation of the algorithm, we observe a twofold speedup for most of the 3D convolution layers of our test network compared to the cuDNN version.

Three-dimensional convolution neural networks (3D CNN) have achieved great success in many computer vision applications, such as video analysis, medical image classification, and human action recognition. However, the efficiency of this model suffers from great computational intensity. In this work, we reduce the algorithmic complexity of 3D CNN to accelerate this model with Winograd’s minimal algorithm. We benchmark a net model on GPU platform, resulting in a speed-up by a factor of 1.2\(\times \) compared with cuDNN, which is commonly used in many current machine learning frameworks.

Nowadays, the rapid growth of data across the Internet has provided sufficient labeled data to train deep structured artificial neural networks. While deeper structured networks bring about significant precision gains in many applications, they also pose an urgent demand for higher computation capacity at the expense of power consumption. To this end, various FPGA based deep neural network accelerators are proposed for higher performance and lower energy consumption. However, as a dilemma, the development cycle of FPGA application is much longer than that of CPU and GPU. Although FPGA vendors such as Altera and Xilinx have released OpenCL framework to ease the programming, tuning the OpenCL codes for desirable performance on FPGAs is still challenging. In this paper, we look into the OpenCL implementation of Convolutional Neural Network (CNN) on FPGA. By analysing the execution manners of a CPU/GPU oriented verision on FPGA, we find out the causes of performance difference between FPGA and CPU/GPU and locate the performance bottlenecks. According to our analysis, we put forward a corresponding optimization method focusing on external memory transfers. We implement a prototype system on an Altera Stratix V A7 FPGA, which brings a considerable 4.76\(\times \) speed up to the original version. To the best of our knowledge, this implementation outperforms most of the previous OpenCL implementations on FPGA by a large margin.

Today&rsquo, s cloud-based online services are underpinned by distributed key-value stores (KVSs). Keys and values are distributed across back-end servers in such scale-out systems. One primary real-life performance bottleneck occurs when storage servers suffer from load imbalance under skewed workloads. In this paper, we present KVSwitch, a centralized self-managing load balancer that leverages the power and flexibility of emerging programmable switches. The balance is achieved by dynamically predicting the hot items and by creating replication strategies according to KVS loading. To overcome the challenges in realizing KVSwitch given the limitations of the switch hardware, we decompose KVSwitch&rsquo, s functions and carefully design them for the heterogeneous processors inside the switch. We prototype KVSwitch in a Tofino switch. Experimental results show that our solution can effectively keep the KVS servers balanced even under highly skewed workloads. Furthermore, KVSwitch only replicates 70 % of hot items and consumes 9.88 % of server memory rather than simply replicating all hot items to each server.

This paper investigates the 3D object retrieval problem by adapting a Convolution Network and introduce triplet loss into the training process of network. The 3D objects are converted to vexolized volumetric grids and then fed into the network. The outputs from the first full connection layer are taken as the 3D object descriptors. Triplet loss is designed to make the learned descriptors more suitable for retrieval. Experiments demonstrate that our descriptors are distinctive for objects from different categories and similar among those from the same category. It is much better than traditional handcrafted features like SPH and LFD. The superiority over another deep network based method ShapeNets validates the effectiveness of the triplet loss in driving same-class descriptors to assemble and different-class ones to disperse.