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Flexible stretch-bending of multi-point roller dies technology is a new three-dimensional forming technology for profiles. Compared with the traditional stretch-bending process, the three-dimensional deformation of the profile can be formed at one time, and the cost of the die is greatly reduced and the production efficiency is improved. The die is an important component of flexible stretch-bending of multi-point roller dies equipment. Discrete die is the focus of this paper. The finite element model of flexible stretch-bending of multi-point roller dies is established. Taking T-profile and L-profile as research objects, the effect of die arrangement on strain, shape error, thickness distribution, and springback error is studied. The non-contact area between profile and die is one of the important factors that affect the 3D deformation of profile. By comparing the numerical simulation results with the experimental results, the effect of the non-contact area length on the three-dimensional deformation of profile is analyzed. The results show that with the increase of the non-contact area length, the shape error of profile increases, the thickness of profile web becomes thinner more seriously, and the springback error of profile increases after unloading.

Springback compensation is considered as the best method to reduce springback error. In view of the springback defect of 3D deformed workpiece, a springback compensation method based on variable compensation factor is proposed. This method can accelerate the convergence speed of iterative compensation. In this paper, the 3D flexible stretch bending of multi-point roller die technology (3D FSB-MPRD) is introduced firstly, and then, the principle of the springback compensation method based on variable compensation factor is explained. In order to improve the springback compensation accuracy of workpiece, the total springback compensation process is divided into horizontal bending springback compensation and vertical bending springback compensation. Taking the T-shaped profile with variable curvature as the research object, the die surface is optimized and the optimal springback compensation factor is obtained by using numerical simulation after multiple iterations. Finally, the results of springback compensation are compared with the desired shape. And the effectiveness of the springback compensation method based on variable compensation factor is verified by comparing the simulation results with the test results.

With the increasing demand of the parts with multi-segment curvature, long length, and complex section shape, the required target shape is more and more difficult to meet. In this article, a flexible three-dimensional (3D) multi-point stretch bending processing method for a roller die is proposed, and a flexible 3D stretch bending equipment of a roller die is developed. With the application of flexible 3D stretch bending technology of roller dies, the complex 3D parts can be formed at one time with only two degrees of freedom. In order to better evaluate the springback deformation of 3D parts, the total springback process of the flexible 3D stretch bending parts of a roller die is divided into two parts: horizontal bending springback distance and vertical bending springback distance. The springback law of different length profiles is studied by numerical simulation and compared with the experiment. From the perspective of springback, this study analyzes the parts produced by the 3D FSBRD process and studies the influence of different process parameters on springback.

Resistive random access memory device (RRAM) has been widely used in various novel circuit systems, such as memory, artificial intelligence, and neural networks, due to its unique memory characteristics. However, there are very few studies focusing on analytic modeling of RRAM. In this article, modeling for solving analytic approximate solution to the state variable of RRAM, based on the proposed Multistage Homotopy Analysis Method (MuHAM), is proposed. Different from traditional HAM, the time span under consideration is divided into many subintervals, then the convergence control parameter in each subinterval is optimized to achieve high approximation accuracy. By simulating and comparing the obtained analytic solutions with solutions solved by other traditional homotopy-based modeling methodologies and by numerical analyses, we verified that MuHAM has higher Quality Factor (introduced to evaluate the model accuracy and computational cost comprehensively), hence improving the simulation efficiency. Besides the classical Hewlett-Packard (HP) RRAM, some current RRAMs are also verified. MuHAM also has the advantages of enabling both qualitative and quantitative analyses, and immunity to convergence issues. It is particularly suitable for the analytic modeling of the other novel memory devices having strong nonlinearity.

Roll forming is an important processing method for the production of commercial vehicle anticollision beams, and edge buckling is one of the common defects in roll-forming process. In this paper, the “日” shape section of roll forming is studied, and first the b-shaped section is formed by roll forming, and the internal weld line is automatically welded while forming; then the long side of the b-shaped section is bent into the “U” shape, and the external weld line is welded while forming. The profile is cut off and then bent at both ends to form a commercial vehicle anticollision beam. The ABAQUS finite element software is used to model and analyze the factors affecting the “edge buckling” defect of roll-formed products. This paper uses three factors and three levels of orthogonal simulation experiments to study the problem. The results show that the effect of the factors of flange height, sheet thickness, and forming speed on the formation of edge buckling is in the order of sheet thickness > flange height > forming speed. The edge buckling size of the vertical edge of b-shaped tube decreases with the increase of sheet thickness and increases with the increase of flange height.

Springback is a common defect caused by elastic recovery in the plastic forming process, which can cause the formed workpiece to deviate from the target shape. The purpose of this paper is to grasp the influence law of process parameters on springback deviation so as to optimize process parameters to reduce springback. Taking the Y-profile as the research object, the influence of process parameters such as horizontal bending radius, vertical bending radius, transition zone length, radius of roller dies, and wall thickness of the profile on springback deviation is discussed by numerical simulation. Additionally, the validity of the numerical simulation is verified through experiments. The springback law obtained by numerical simulation is applied to practical production, and the large-scale production of the Y-profile is realized.

Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters.

Timing optimization for logic circuits is one of the key steps in logic synthesis. Extant research data are mainly proposed based on various intelligence algorithms. Hence, they are neither comparable with timing optimization data collected by the mainstream electronic design automation (EDA) tool nor able to verify the superiority of intelligence algorithms to the EDA tool in terms of optimization ability. To address these shortcomings, a novel verification method is proposed in this study. First, a discrete particle swarm optimization (DPSO) algorithm was applied to optimize the timing of the mixed polarity Reed-Muller (MPRM) logic circuit. Second, the Design Compiler (DC) algorithm was used to optimize the timing of the same MPRM logic circuit through special settings and constraints. Finally, the timing optimization results of the two algorithms were compared based on MCNC benchmark circuits. The timing optimization results obtained using DPSO are compared with those obtained from DC, and DPSO demonstrates an average reduction of 9.7% in the timing delays of critical paths for a number of MCNC benchmark circuits. The proposed verification method directly ascertains whether the intelligence algorithm has a better timing optimization ability than DC.

High precision and smart sensors make up an indispensable data entry for the Internet of Things technology. Nonetheless, conventional calibration algorithms mainly implemented on the software, such as least squares, polynomial fitting, and interpolation, exhibit limited calibration accuracy that does not reflect a real-time measurement of the sensors. The problem can be resolved with an MCU-based sensor calibration system proposed herein, which mainly employs particle swarm optimization (PSO)-back propagation (BP) neural network. The system firstly reads sensor data through I2C bus and then uses the BP neural network and PSO algorithm to automatically calibrate these data in real time. Sigmoid activation function was implemented via a piecewise polynomial fitting to create a trade-off between hardware resource and precision. A performance test conducted on temperature sensors showed a maximum error of 0.16 °C within the measurement range of −40–100 °C with three times the standard deviation (3 σ ) error of ±0.23 °C and overall linearity of 0.1143% after the calibration system was added as compared to the significantly higher error of ±0.63 °C without the calibration.

This work proposes a novel amplitude modulation topology which including a recently discovered unique memory element — memristor. The circuit is validated by theoretical analyses and simulations that generating a standard amplitude modulation signal with no harmonic component. Our results support the feasibility that memristor can be applied to communication circuit.

Based on the model of memeristor fabricated at HP laboratory, a new multiplexed flip-flop is proposed which can support power-off mode for scan testing. Testing data can be stored in memristor during the power-off time. The analyzes are verified with SPICE simulation, signal waveforms show that the presented memristive multiplexed flip-flop meet the requirements for low-power scan testing.