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Today, the number of Internet of Things (IoT) devices in all aspects of life is increasing exponentially. Our cities are getting smarter and informing us about our surroundings in a contextual manner. However, we face significant challenges in deploying, managing, and collecting data from these devices. In addition, we must address the problem of storing and mining that data for higher-quality IoT services. Blockchain technology, even in today's nascent form, has the potential to be the foundation for a common, distributed, trustless, and autonomous infrastructure system. This article describes a standardized IoT infrastructure where data are stored on a distributed storage service that is fault-tolerant and resistant to distributed denial of service (DDOS) attacks and data access is managed by a decentralized, trustless blockchain. The illustrated system used LoRa as the emerging network technology, Swarm as the distributed data storage platform, and Ethereum as the blockchain platform. Such a data back end will ensure high availability with minimal security risks while replacing traditional back-end systems with a single "smart contract."

Every year, a massive number of deaths happen because of traffic accidents. In order to increase the traffic victim’s survival rates, it is important to reduce the arrival time of medical and trauma intervention teams to accidents’ sites. Automatic incident detection provides faster incident reporting to decrease the delay of arrival time of first responders. In this paper, we propose a roadside unit (RSU) that automatically detects traffic incidents using multiple detection mechanisms, verifies to reduce false alarms and reports to the intelligent traffic management system. The proposed RSU is modeled in Architecture Analysis and Design Language (AADL). Simulation results show that our RSU model is schedulable with low processor utilization factors, and provides incident detection and reporting in under three minutes.

We are proposing a Customizable Embedded Processor Array for Multimedia Applications (CPAMA). This architecture can be used as a standalone image/video processing chip in consumer electronics. Its building blocks are all designed to achieve low power and low area, thus it is a good candidate for low cost consumer electronics. Our contribution is, designing a configurable embedded multimedia processor array considering the nature of image/video processing applications. This approach is considered in all the basic blocks of the architecture. Because of its configurable architecture and ability to connect with other devices, it may be used in a large domain of applications. Our architecture is purely implemented with VHDL. It is not dependent on any technology or design software. We have implemented our architecture for different applications on a Xilinx Virtex-5 device and as a number of Application Specific Integrated Circuits (ASIC) by using 90 nm CMOS technology. Experimental case studies show that CPAMA has better or comparable results to the existing similar architectures in terms of performance and energy consumption. Our studies show that throughput of CPAMA is 0.3x–2.4x times better than ADRES. Energy consumption of CPAMA is 31–50% less than ADRES. On the other hand, in one configuration of IDCT application, CPAMA provides 56% less throughput and consumes 55% more energy than ADRES.

With the rise of Internet of Things (IoT), low-cost resource-constrained devices have to be more capable than traditional embedded systems, which operate on stringent power budgets. In order to add new capabilities such as learning, the power consumption planning has to be revised. Approximate computing is a promising paradigm for reducing power consumption at the expense of inaccuracy introduced to the computations. In this paper, we set forth approximate computing features of a processor that will exist in the next generation low-cost resource-constrained learning IoT devices. Based on these features, we design an approximate IoT processor which benefits from RISC-V ISA. Targeting machine learning applications such as classification and clustering, we have demonstrated that our processor reinforced with approximate operations can save power up to 23% for ASIC implementation while at least 90% top-1 accuracy is achieved on the trained models and test data set.

As embedded systems have evolved to appear in many different domains, symmetric multiprocessing (SMP) has been the design choice from low-end to high-end devices. In this paper we present Prenaut, a design space exploration method for finding the best on-chip SMP architectures given processor cores, Level 1, Level 2, and Level 3 caches. Unlike traditional design space exploration tools that are majorly concerned with optimizations in processor, memory and cache structures with a fixed on-chip architecture, Prenaut explores architectures that have not been considered in symmetric multiprocessing domain. These architectures consist of shared instruction caches between cores and heterogeneous cache topologies that feature bypassing a level in the cache hierarchy. The design idea behind Prenaut is to build a data oriented design space exploration method that exploits simulation data to its full extent rather than discarding it. Therefore, Prenaut uses simulation data and applies machine learning methods for estimating design parameters. This provides very rapid estimation of the Pareto set and guides designers through the overall system design process. The design space is pruned by topological clustering of design points which groups similar topologies and new simulation points are selected via an ordered look up table that prevents infeasible random jumps in the design space. For the selected benchmarks, Prenaut can estimate the Pareto set up to 147x faster and the clustering information can reduce the design space up to 82% in comparison with a state-of-the-art evolutionary algorithm.

An integrated circuit contains millions of components, all of which have to fit in the reserved silicon area and fulfill a defined functionality within a specified amount of execution time. Therefore, the design of an effective integrated circuit is a nontrivial task. Actually, it can be considered as a multi-objective optimization problem with two conflicting objectives: minimizing the total execution time called latency and the total silicon area of the integrated circuit. The overall problem is composed of tightly-coupled subproblems, i.e., determining the allocation of operators that execute the operations, the assignment of operations to operators, and scheduling of the operations. We formulate a multi-objective mixed-integer linear programming model (MOMILP) to solve this complex problem. It is novel since it incorporates decisions about the so-called multiplexers, which are essential components of an integrated circuit. The proposed MOMILP model is solved exactly using an augmented e-constrained method. This enables us to find all the Pareto optimal solutions and hence the Pareto frontier for a given problem instance within a reasonable amount of computation time. The minimum latency and minimum area solutions of our model are 13.20 and 7.24% better on the average than the model that ignores multiplexers.

Today, Internet of Things (IoT) devices are the powerhouse of data generation with their ever-increasing numbers and widespread penetration. Similarly, artificial intelligence (AI) and machine learning (ML) solutions are getting integrated to all kinds of services, making products significantly more "smarter". The centerpiece of these technologies is "data". IoT device vendors should be able keep up with the increased throughput and come up with new business models. On the other hand, AI/ML solutions will produce better results if training data is diverse and plentiful. In this paper, we propose a blockchain-based, decentralized and trustless data marketplace where IoT device vendors and AI/ML solution providers may interact and collaborate. By facilitating a transparent data exchange platform, access to consented data will be democratized and the variety of services targeting end-users will increase. Proposed data marketplace is implemented as a smart contract on Ethereum blockchain and Swarm is used as the distributed storage platform., Comment: Presented at Crypto Valley Conference on Blockchain Technology (CVCBT 2018), 20-22 June 2018 - published version may differ

The ever-increasing number of IoT devices necessitates a secure and scalable infrastructure to store and process generated data. Blockchain is an ideal choice with its decentralized, trustless architecture. However, low-power IoT end-devices do not possess enough horsepower to run a software client for intensive blockchain calculations. The purpose of this paper is to create a proof of concept to enable low-power, resource-constrained IoT end-devices accessing a blockchain-based infrastructure. To achieve this aim, an IoT gateway is configured as a blockchain node and an event-based messaging mechanism for low-power IoT end-devices is proposed. A demonstration of such a system is realized using LoRa nodes and gateway in a private Ethereum network.

As Network-on-Chips (NoC) are the most scalable architecture with growing number of processing elements in multi-core systems, communication data between nodes tend to travel through more routers. Hence, a good mapping algorithm must be designed in order to locate most communicating nodes neighbour to each other. However, this may not be sufficient for data-intensive applications such as audio, video, telecommunication and etc. In such multi-core applications, processing elements communicate to each other with heavy load statically in most cases. Passing heavy load data through routers might make the routers bottleneck of the system. In this paper, we propose a custom 2-D NoC architecture with simple reconfigurable switches, which can be configured during both design and runtime according to the application requirements. We designed a mapping algorithm which tries to set paths through these simple switches instead of complicated routers all the way. Experimental results show that our mapping algorithm reduces routing cost up to by 79.96% for real life embedded applications.

Recent years have seen a new generation of HLS tools, which do not only allow to generate hardware architectures from hardware behavioral models, but perform synthesis starting from algorithms specified in HLLs. One of the reasons for this development is the ever growing popularity of reconfigurable logic, which aims at providing the performance and energy efficiency of integrated circuits at a flexibility that is very close to software.

With the rise of Big Data, providing high-performance query processing capabilities through the acceleration of the database analytic has gained significant attention. Leveraging Field Programmable Gate Array (FPGA) technology, this approach can lead to clear benefits. In this work, we present the design and implementation of AxleDB: An FPGA-based platform that enables fast query processing for database systems by melding novel database-specific accelerators with commercial-off-the-shelf (COTS) storage using modern interfaces, in a novel, unified, and a programmable environment. AxleDB can perform a large subset of SQL queries through its set of instructions that can map compute-intensive database operations, such as filter, arithmetic, aggregate, group by, table join, or sort, on to the specialized high-throughput accelerators. To minimize the amount of SSD I/O operations required, AxleDB also supports hardware MinMax indexing for databases. We evaluated AxleDB with five decision support queries from the TPC-H benchmark suite and achieved a speedup from 1.8X to 34.2X and energy efficiency from 2.8X to 62.1X, in comparison to the state-of-the-art DBMS, i.e., PostgreSQL and MonetDB. The research leading to these results has received funding from the European Union Seventh Framework Program (FP7) (under the AXLE project GA number 318633), the Ministry of Economy and Competitiveness of Spain (under contract number TIN2015-65316-p), Turkish Ministry of Development TAM Project (number 2007K120610), and Bogazici University Scientific Projects (number 7060).