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A dual-channel multiplier (DCM) for energy efficient second-order piecewise-polynomial function evaluation for 3-D graphics applications is presented in this paper. The performance of the evaluation process is highly dependent on the design of the multiplication and squaring structure. A novel hardware implementation for polynomial evaluation is presented. The proposed approach compensates the complex multipliers by using DCM which reduces the hardware complexity. The DCM scheme performs complex functions with power-efficient and area-efficient approach. The multiplier reduces the hardware computational effort in the piecewise polynomial approximation with uniform or nonuniform segmentation. For large operand input size, a multiplier adder converter and a dedicated radix-4 squaring unit are also proposed. These units achieve the least power consumption compared to previous approaches with large input word size. Comparison with general purpose multiplication has shown reduction in power, and delay by up to 36%, and 50%, respectively. The proposed technique exhibits up to 93% saving in power consumption compared to the current traditional schemes.

Deep brain stimulation (DBS) electrodes have been proved to be effective in treating neural related diseases in rodents. These devices were successfully extended to the field of human neuro therapy. Many different electrodes exist. However, no quantitative ranking criterion is available to allow meaningful comparison of the various DBS electrodes to aid the designer.This paper presents a novel Figure of Merit (FOM) dedicated to DBS electrodes. The proposed optimization performance takes into account safety factors of mechanical analysis and the estimated fabrication cost of some materials. The FOM is used to rank several DBS electrode designs.Finite Element Models (FEM) analysis for several electrode layouts are conducted. FEM shows the effects of different design parameters on the electrode mechanical performance. These parameters include electrode dimensions, geometry, and materials. The electrodes mechanical analysis is evaluated from different points of view including: linear buckling analysis, stationary analysis with axial and shear loading. The safety factors are calculated for several designs with different materials (brittle and ductile materials). The results obtained from FEM mechanical analysis for the various electrodes prototypes are presented, which provide guidelines for different electrode designs and material choice. A proposed fabrication process along with an estimated fabrication cost is also introduced.

An energy efficient double logarithmic arithmetic (DLA) technique is proposed for 3-D graphics applications. DLA manipulates the logarithmic arithmetic and improves the architecture for the realization of the transcendental functions and the advanced lighting model using energy efficient techniques. The DLA features complete elimination of multipliers in logarithmic domain by using successive logarithmic converters. DLA demonstrates up to 56% reduction in power consumption as compared to the existing techniques. The main advantage of this approach is the ability to perform the complex functions using power-efficient, area-efficient, as well as high frequency design. The proposed technique performs transcendental functions using multiplier free hardware architecture. Moreover, based on nonuniform subdivisions and piecewise linear approximation, novel logarithmic and antilogarithmic converters are also proposed. These converters achieve optimal power consumption as compared to several recent approaches. The proposed converters provide low relative error with less nonuniform subdivisions. Up to 19%, 12%, and 20% reduction in relative error, area, and power consumption are achieved, respectively.

This paper presents a proposed design for analyzing electrocardiography (ECG) signals. This methodology employs highpass least-square linear phase Finite Impulse Response (FIR) filtering technique to filter out the baseline wander noise embedded in the input ECG signal to the system. Discrete Wavelet Transform (DWT) was utilized as a feature extraction methodology to extract the reduced feature set from the input ECG signal. The design uses back propagation neural network classifier to classify the input ECG signal. The system is implemented on Xilinx 3AN-XC3S700AN Field Programming Gate Array (FPGA) board. A system simulation has been done. The design is compared with some other designs achieving total accuracy of 97.8%, and achieving reduction in utilizing resources on FPGA implementation.

The new field of neuro-prosthetics focuses on the design and implementation of neural prostheses to restore some of the lost neural functions. The electrode-tissue contacts remain one of the major obstacles of neural prostheses microstructure. Recently, Microelectrode fabrication techniques have been developed to have a long-term and stable interface with the brain. In this paper, a comparative analysis of finite element models (FEM) for several electrode layouts is conducted. FEM involves parametric and sensitivity analysis to show the effects of the different design parameters on the electrode mechanical performance. These parameters include electrode dimensions, geometry, and materials. The electrodes mechanical performance is evaluated with various analysis techniques including: linear buckling analysis, stationary analysis with axial and shear loading, and failure analysis for brittle and ductile materials. Finally, a novel figure of merit (FOM) is presented and dedicated to the various electrodes prototypes. The proposed designs take into account mechanical performance, fabrication cost, and cross sectional area of the electrode. The FOM provides important design insights to help the electrodes designers to select the best electrode design parameters that meet their design constraints.

An efficient manipulation of the logarithmic number system (LNS) is proposed resulting in saving in power and area of graphical processing unit (GPU). Double Logarithmic Arithmetic (DLA) approach is presented to achieve low power applications. The proposed scheme exploits the logarithmic field and enhances the computation of the transcendental operations and the lighting pattern operations for energy and area efficiency. The DLA is exploited by means of cascading logarithmic converters to completely eliminate multipliers. Comparison results show that this work achieves up to 51% saving in power and 40% area reduction as compared to the current schemes. The proposed methodology can implement all the transcendental processes utilizing multiplier-free hardware structural.

Logarithmic number system (LNS) is increasingly used for low power arithmetic calculations in graphical processing unit (GPU). LNS requires less hardware. Based on uniform subdivisions and linear-Lagrange interpolation, a novel 8-subdivisions logarithmic/antilogarithmic converters are proposed. Compared with different methodologies, the proposed logarithmic/antilogarithmic converters achieve high accuracy. Also, a significant decrease in area is presented in the comparison between the proposed converters and the prior ones. Hardware implementation using shift-and-add approach is adopted to further simplify the hardware. The novel logarithmic/antilogarithmic converters are implemented and synthesized using 90 nm CMOS technology. Up to 23% and 11% decrease in relative error and area are achieved.

In this paper, we designed and fabricated a high performance, low power image processing unit for payload camera subsystem for a nano satellite. The nano satellite has very limited power source produced from solar panels as the dimension of this panel is 10×10 cm. The camera system is the most subsystem in the satellite, which consumes high power during the image processing stage. We presented, a low power architecture for the matrix — vector multiplier of a constant matrix by a vector, which transforms the main part of the Discrete Cosine (DCT) in the compression circuit of an image unit. The image processing unit has been designed using FPGA technology, lower power is achieved on the architectural level. We have fabricated the PCB using FPGA (SPARTAN 3E 200), with SD Card for image storage and EEPROM for FPGA programming. This PCB is 4 layers and is designed with miniature dimensions to be more reliable and can be easily installed in the nano satellite inside camera module.