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The standard and layout-hardened D filp-flops (DFFs) named DFF1–6 were designed and manufactured based on an advanced 22-nm ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) technology. Heavy-ion irradiation results indicate that FD-SOI technology has contributions to radiation hardness and the hardened DFFs have higher single-event upset (SEU) tolerance than the standard DFF. The upsets induced by the embedded SET targets are strongly dependent on the testing frequency. The layout separating the dual interlocked storage cell (DICE) structure can prevent the direct occurrence of SEU in flip-flop cells, and upsets were removed completely in two-fold DICE structure DFFs.

The interaction of radiation with three-dimensional (3D) electronic devices can be determined through the detection of single-event effects (SEU). In this study, we propose a method for the evaluation of SEUs in 3D static random-access memories (SRAMs) induced by heavy-ion irradiation. The cross-sections (CSs) of different tiers, as a function of the linear energy transfer (LET) under high, medium, and low energy heavy-ion irradiation, were obtained through Monte Carlo simulations. The simulation results revealed that the maximum value of the CS was obtained under the medium-energy heavy-ion penetration, and the effect of penetration range of heavy ions was observed in different tiers of 3D-stacked devices. The underlying physical mechanisms of charge collection under different heavy-ion energies were discussed. Thereafter, we proposed an equation of the critical heavy-ion range that can be used to obtain the worst CS curve was proposed. Considering both the LET spectra and flux of galactic cosmic ray (GCR) and the variation in the heavy-ion Bragg peak values with the atomic number, we proposed a heavy-ion irradiation test guidance for 3D-stacked devices. In addition, the effectiveness of this method was verified through simulations of the three-tier vertically stacked SRAM and the ultrahigh-energy heavy-ion irradiation experiment of the two-tier vertically stacked SRAM. this study provides a theoretical framework for the detection of SEUs induced by heavy-ion irradiation in 3D-integrated devices.

Using the heavy ions provided by the Heavy Ion Research Facility in Lanzhou (HIRFL), the annealing of heavy-ion induced floating gate (FG) errors in 34 nm and 25 nm NAND Flash memories has been studied. The single event upset (SEU) cross section of FG and the evolution of the errors after irradiation depending on the ion linear energy transfer (LET) values, data pattern and feature size of the device are presented. Different rates of annealing for different ion LET and different pattern are observed in 34 nm and 25 nm memories. The variation of the percentage of different error patterns in 34 nm and 25 nm memories with annealing time shows that the annealing of FG errors induced by heavy-ion in memories will mainly take place in the cells directly hit under low LET ion exposure and other cells affected by heavy ions when the ion LET is higher. The influence of Multiple Cell Upsets (MCUs) on the annealing of FG errors is analyzed. MCUs with high error multiplicity which account for the majority of the errors can induce a large percentage of annealed errors.

Single event effects of 1-T structure programmable read-only memory (PROM) devices fabricated with a 130-nm complementary metal oxide semiconductor-based thin/thick gate oxide anti-fuse process were investigated using heavy ions and a picosecond pulsed laser. The cross sections of a single event upset (SEU) for radiation-hardened PROMs were measured using a linear energy transfer (LET) ranging from 9.2 to 95.6 MeV cm2 mg−1. The result indicated that the LET threshold for a dynamic bit upset was ~ 9 MeV cm2 mg−1, which was lower than the threshold of ~ 20 MeV cm2 mg−1 for an address counter upset owing to the additional triple modular redundancy structure present in the latch. In addition, a slight hard error was observed in the anti-fuse structure when employing 209Bi ions with extremely high LET values (~ 91.6 MeV cm2 mg−1) and large ion fluence (~ 1 × 108 ions cm−2). To identify the detailed sensitive position of a SEU in PROMs, a pulsed laser with a 5-μm beam spot was used to scan the entire surface of the device. This revealed that the upset occurred in the peripheral circuits of the internal power source and I/O pairs rather than in the internal latches and buffers. This was subsequently confirmed by a 181Ta experiment. Based on the experimental data and a rectangular parallelepiped model of the sensitive volume, the space error rates for the used PROMs were calculated using the CREME-96 prediction tool. The results showed that this type of PROM was suitable for specific space applications, even in the geosynchronous orbit.

The 65 nm Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) was designed and manufactured, which employed tradeoff radiation hardening techniques in Configuration RAMs (CRAMs), Embedded RAMs (EBRAMs) and flip-flops. This radiation hardened circuits include large-spacing interlock CRAM cells, area saving debugging logics, the redundant flip-flops cells, and error mitigated 6-T EBRAMs. Heavy ion irradiation test result indicates that the hardened CRAMs had a high linear energy transfer threshold of upset &sim, 18 MeV/(mg/cm 2 ) with an extremely low saturation cross-section of 6.5 &times, 10 &minus, 13 cm 2 /bit, and 71% of the upsets were single-bit upsets. The combinational use of triple modular redundancy and check code could decline &sim, 86.5% upset errors. Creme tools were used to predict the CRAM upset rate, which was merely 8.46 &times, 15 /bit/day for the worst radiation environment. The effectiveness of radiation tolerance has been verified by the irradiation and prediction results.

Radiation effects can induce severe and diverse soft errors in digital circuits and systems. A Xilinx commercial 16 nm FinFET static random-access memory (SRAM)-based field-programmable gate array (FPGA) was selected to evaluate the radiation sensitivity and promote the space application of FinFET ultra large-scale integrated circuits (ULSI). Picosecond pulsed laser and high energy heavy ions were employed for irradiation. Before the tests, SRAM-based configure RAMs (CRAMs) were initialized and configured. The 100% embedded block RAMs (BRAMs) were utilized based on the Vivado implementation of the compiled hardware description language. No hard error was observed in both the laser and heavy-ion test. The thresholds for laser-induced single event upset (SEU) were ~3.5 nJ, and the SEU cross-sections were correlated positively to the laser&rsquo, s energy. Multi-bit upsets were measured in heavy-ion and high-energy laser irradiation. Moreover, latch-up and functional interrupt phenomena were common, especially in the heavy-ion tests. The single event effect results for the 16 nm FinFET process were significant, and some radiation tolerance strategies were required in a radiation environment.