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We present a novel cavity engineering work – we named this cavity as dual-curvature cavity, which improves pFET electrical performance. This new cavity shape design minimizes the source/drain leakage penalty from deeper cavity depth while enabling the transistor performance benefits from larger eSiGe. In addition, this new cavity shape minimizes the penalty of deeper cavity on SDB (single diffusion break) devices through minimizing the facet effect in SDB structure. This work demonstrates that this new cavity shape could improve p-type transistor performance by 4{\%} on top of the Fin shape optimization.

We present a method to form a spacer-confined cavity to enable the deeper cavity for performance improvement while keeping the lateral width of epitaxial silicon doped with phosphorous (SiP EPI) from creating an EPI bridging issue. An extra non-selective etch step is introduced to leave the sidewall spacer but etch away the Si fin. The SiP EPI is confined between the sidewall spacer for EPI lateral width control. In this work, TCAD simulation shows that the effective gate length (Leff) near the bottom of the fin decreases when cavity depth increases. The deeper junction provides another performance boost on top of the performance improvement from the fin height increase. In addition, the spacer-confined cavity demonstrates a 6% device performance improvement with comparable drain-induced-barrier-lowering at +8 nm cavity depth. The device performance starts saturation when the cavity depth extends beyond +15 nm. The spacer-confined cavity offers a solution to increase cavity depth without suffering from the EPI bridging issue for advance finFET technology.