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This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied. At liquid nitrogen temperatures, 30% to 200% enhancement of drain current, Id, and maximum transconductance, gm_max, values are demonstrated. Current gain cutoff frequency, fT, increase by about 85 GHz is shown. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This study suggests 28 nm FDSOI as a good contender for future read-out electronics operated at cryogenic temperatures (as e.g. around qubits or in space).

This work investigates the low-frequency noise performance of a long-channel UTBB FD SOI nMOS transistor operated in triode region as typically used for MOSFET-C filter applications. Measurements of the low-frequency noise have been performed over a large temperature range (25–125°C) at different constant currents above threshold, as a function of the back-gate bias. It is highlighted that in such case, 1/f noise power is dominant, however sufficiently low, in the frequency range of interest for the filters, i.e. below 1 MHz. Noise power strongly reduces with temperature and slightly with positive back-gate bias, which is adequate for the filter tuning.

This work provides a detailed study of 28 nm fully-depleted silicon-on-insulator (FD-SOI) planar ultra-thin body and BOX (UTBB) MOSFETs for high frequency applications. All parasitic elements such as the parasitic gate and source/drain series resistances, total capacitances are extracted and their effects on RF performance are analyzed and compared with previous work on similar devices. Two main RF figures of merit (FoM) such as the current gain cut-off frequency ( f T ) and the maximum oscillation frequency ( f max ) are determined. It is shown that f T of ∼280 GHz and f max of ∼250 GHz are achievable in the shortest devices. Based on the extracted parameters, the validation of the small-signal equivalent circuit used for modeling UTBB MOSFETs is investigated by comparing simulated and measured S -parameters.

This work presents a detailed RF characterization of 28 FDSOI nMOSFETs at cryogenic temperatures down to 4.2 K. Two main RF Figures of Merit (FoMs), i.e. current gain cutoff frequency (f T ) and maximum oscillation frequency (f max ), as well as parasitic elements of the small-signal equivalent circuit are extracted from the measured S-parameters. The observed behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This study suggests 28 FDSOI nMOSFETs as a good candidate for future cryogenic applications down to 4.2 K and clarifies the origin and limitations of the performance.

This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied for the first time to our best knowledge. At cryogenic temperatures, 20–70% enhancement of drain current, Id, and maximum transconductance, gm_max, values as well as up to 100 GHz increase of cut-off frequency, fT, are demonstrated. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This first study suggests 28FDSOI as a good contender for future read-out electronics around qubits.

In this work three different types of UNIBOND™ Silicon-on-Insulator (SOI) wafers including one standard HR-SOI and two types of trap-rich high resistivity HR-SOI substrates named enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) provided by SOITEC are studied and compared. The DC and RF performances of these wafers are compared by means of passive and active devices such as coplanar waveguide (CPW) lines, crosstalk- and noise injection-structures as well as partially-depleted (PD) SOI MOSFETs. It is demonstrated that by employing enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) compared to HR-SOI wafer, a reduction of 24 dB is measured on both generations of trap-rich HR-SOI for 2nd harmonics. Furthermore, it is shown that in eSI HR-SOI, digital substrate noise is effectively reduced compared with HR-SOI. Purely capacitive behavior of eSI HR-SOI is demonstrated by crosstalk structure. Reduction of self-heating effect in the trap-rich HR-SOI with thinner BOX is finally studied.

In this work 3 different types of UNIBOND™ Silicon-on-Insulator (SOI) wafers including one standard and two types of trap-rich high resistivity HR-SOI substrates provided by SOITEC are studied. The DC and RF performances of these wafers are compared by means of passive and active devices, coplanar waveguide (CPW) lines and partially-depleted (PD) SOI MOSFETs, respectively.

This work investigates experimentally the non-linearities of FDSOI MOSFETs from DC to RF frequencies. The effect of the back-gate bias on non-linearity of the device is studied by means of 2nd and 3rd harmonic distortions (HD2 and HD3) extracted from dc I-V curves as well as from large-signal RF measurements using 1-dB and IP3 points. It is shown that the non-linearity is reduced by applying a positive back-gate bias. The reasons for this reduction are increasing of “effective body factor” and lesser mobility degradation with increase of the positive back-gate bias.