Search

We demonstrate a novel process for building a Resistive RAM (ReRAM) stack which reduces the forming voltage ( $\text{V}_{\textit {form}}$ ) and increases the switching resistance, both characteristics that are important ingredients for the use of ReRAM in scalable analog compute for AI. Utilizing this process, we explore analog switching characteristics above 100k $\Omega $ and demonstrate 4-bit programming at Rmax $=1\text{M}\Omega $ . Utilizing the same writing characteristics, CIFAR-10 inference simulation shows 90% accuracy, comparable to the full precision model accuracy.

High endurance ovonic threshold switch (OTS, here, TeAsGeSiSe-based) is integrated with phase change memory (PCM, here, doped Ge2Sb2Te5) to form a 3-D stackable pillar-type device. With the help of an etch buffer layer and a damage-free pillar reactive-ion etching process, we successfully demonstrate one-selector (OTS)/one-resistor (PCM) (1S1R OTS-PCM) pillar device without OTS/PCM composition modification. High temperature 400 °C annealing tests show this 1S1R OTS-PCM pillar device is back end of line compatible. We report the fundamental behavior of the OTS and the operation scheme of the 1S1R OTS-PCM device. The new Vth read scheme is proposed and excellent electrical performance is demonstrated. It provides the fast turn ON/ OFF speed which enables 10-ns fast RESET speed. Program endurance greater than 109 cycles is achieved, and read endurance is higher than 1011 cycles.

The Naval Research Laboratory (NRL) has developed a processing system based on an electron beam-generated plasma, where unlike conventional discharges produced by electric fields (DC, RF, microwave, etc.), ionization is driven by a high-energy (~ keV) electron beam. The resulting plasmas are characterized by large electron densities (10 10 –10 11 cm − 3 ) and low electron temperatures (0.3–1.0 eV). Accordingly, a large flux of ions can be delivered to substrate surfaces with kinetic energies of only a few eV, a feature that can be attractive to processing applications that require low damage and atomic layer precision. This work describes the salient features of these plasmas produced in mixtures of argon and sulfur hexafluoride (SF 6 ) and their use in silicon nitride etching, with particular attention paid to developing processing parameters relevant to atomic layer processing.

We demonstrate a CMOS-compatible, metal-oxide based Electro-Chemical Random-Access Memory (MO- ECRAM) for high-speed, low-power neuromorphic computing. The device demonstrates symmetric and linear conductance update, large on/off ratio and good retention while also withstanding high temperature treatments necessary for BEOL compatibility. Resistive switching in MO-ECRAM is observed with voltage pulses down to 10 ns and scales exponentially with voltage pulse amplitude, enabling parallel array operations without any selector/access devices. For the first time, we experimentally demonstrate fundamental techniques for fully- parallel array operations, stochastic update scheme and zero-shifting technique, and show a successful stochastic gradient descent algorithm demonstration in hardware using a MO- ECRAM array.

A baseline TiAl-containing ALD electrode is established, with properties in line with reported workfunction (WF) materials for scaled RMG nFETs, values below 4.6eV requiring a 25A layer. Furthermore, a novel ALD metal-compound material, MX, is shown to enable at least 10A further scaling of the electrode stack due to its superior scavenging power. It can be finely tuned by the film thickness, allowing for a remarkable 20-30meV WF delta per ALD cycle over a minimum 600meV range. The wet etchability of the electrodes makes multi-Vt and dual-WF integration possible. MX does not degrade transfer characteristics and reliability of RMG FinFETs, while the thinner nWF electrode enables reduced gate resistance, as verified down to 20nm metal gate lengths. For the first time, taking advantage of the MX compound scavenging power to control oxygen filaments, we demonstrate an all-ALD HfO 2 -based ReRAM. Forming voltages match those achieved by optimized PVD contacts, while scaling the active electrode thickness by a factor of 4x, down to 5nm. Conformality of the layers enables vertical-ReRAM architectures with reduced line resistance. We conclude the developed electrode can facilitate both logic scaling beyond the 10nm node, and 3D memory technology.

We report InGaAs gate-all-around nanosheet NFETs on Si substrate using template-assisted-selective-epitaxy (TASE) and a gate-last process with thermal budget advantages. Compared to our early report of the TASE process, in this paper we demonstrate that TASE can be scaled to a channel thickness of ∼10 nm, which enables short gate devices without significant leakage. The defects and composition of the fabricated nanosheet FETs are also investigated. Enabled by this VLSI compatible process and a novel high-pressure deuterium annealing process, our 39 nm- $L_{g}$ device shows a peak $g_{m}$ of $1.37 \ \text{mS}/\mu \mathrm{m}$ , a subthreshold slope in saturation of 72 mV/decade, and an $I_{on}$ of $355 \ \mu \mathrm{A}/\mu \mathrm{m}$ at 0.5 V $V_{gs}$ , the highest among reported sub-50 nm- $L_{g}$ III-V FETs on Si.

For the first time published, high endurance OTS (ovonic threshold switch, here, TeAsGeSiSe-based) is integrated with PCM (here, doped Ge2Sb2Te5) to form a 3D stackable pillar type device. With the help of an etch buffer layer and a damage-free pillar RIE process, we achieved 100% array yield without OTS/PCM composition modification. Anneal tests show this one-selector/one-resistor (1S1R) pillar device is BEOL-compatible.We report excellent electrical performance by 1S1R OTS-PCM device; selector provides the fast turn on/off speed which enables 10ns fast RESET speed, program endurance is 109 cycles, and read endurance is higher than 1011 cycles.

The resistivity of damascene Cu is measured at cross-sectional area as low as 95 nm2. The impact of aspect ratio and line edge roughness on resistivity is investigated. Kelvin resistance test structures are demonstrated with 28 nm pitch wires patterned by directed self-assembly of lamellar block copolymers. The effective resistivity of TaN/Ta/Cu wires is compared with alternative metals.

The need for continued device scaling along with the increasing demand for high precision have lead to the development of atomic layer etch processes in semiconductor manufacturing. We have tested this new methodology with regard to patterning applications. While these new plasma-enhanced atomic layer etch (PE-ALE) processes show encouraging results, most patterning applications are best realized by optimizations through discharge chemistry and/or plasma parameters. While PE-ALE approaches seem to have limited success for trilayer patterning applications, significant improvements were obtained when applying them to small pitch. In particular the increased selectivity to OPL seems to offer a potential benefit for patterning high aspect ratio features.

A novel etch chemistry, C4H9F was evaluated for highly selective patterning of SiN using both organic and SiOx masks for line/space and cylindrical geometries. Patterning of 80 nm of SiN using 65 nm of the organic planarization layer (OPL) mask with a C4H9F:O2:CF4 admixture yielded line edge roughness (LER) and line width roughness (LWR) values of 1.9 and 2.8 nm on sub-25 nm critical dimension (CD) SiN lines at 50 nm pitch, with >50 nm mask retention up to 40% overetch values. The LER and LWR values were 60% and 66% lower than features patterned using a CF4:CHF3 admixture, which also exhibited complete OPL mask loss and nitride erosion of 27 nm even at the endpointed etch condition. Using 20 nm of SiOx as a mask and removing CF4 from the chemistry admixture, LER and LWR values of 2.7 and 3.3 nm were achieved with nearly full SiOx retention for features of identical dimensions. At smaller mask pitches (21 and 24 nm) formed by directed self-assembly of high-χ block copolymers, the highly selective nature of C4H9F to organic masks facilitated SiN pattern transfer where CF4 based admixtures failed, achieving line CDs of ∼12 nm with LWR and LER of 1.6 and 2.2 nm. Applied to alternate geometry, hole patterning in SiN at ∼30 nm CD and 60 nm pitch was demonstrated. A subsequent image reversal process yielded pillars by filling the hole pattern with OPL and etching back the surrounding SiN layer, reaffirming the extremely high selectivity of C4H9F to organic masks.A novel etch chemistry, C4H9F was evaluated for highly selective patterning of SiN using both organic and SiOx masks for line/space and cylindrical geometries. Patterning of 80 nm of SiN using 65 nm of the organic planarization layer (OPL) mask with a C4H9F:O2:CF4 admixture yielded line edge roughness (LER) and line width roughness (LWR) values of 1.9 and 2.8 nm on sub-25 nm critical dimension (CD) SiN lines at 50 nm pitch, with >50 nm mask retention up to 40% overetch values. The LER and LWR values were 60% and 66% lower than features patterned using a CF4:CHF3 admixture, which also exhibited complete OPL mask loss and nitride erosion of 27 nm even at the endpointed etch condition. Using 20 nm of SiOx as a mask and removing CF4 from the chemistry admixture, LER and LWR values of 2.7 and 3.3 nm were achieved with nearly full SiOx retention for features of identical dimensions. At smaller mask pitches (21 and 24 nm) formed by directed self-assembly of high-χ block copolymers, the highly selective nature of...

The performance of low-k nitride spacer etch processes for fin-field effect transistor device fabrication was investigated using C4H9F based and CH3F based plasma gas chemistries. C4H9F showed a larger process window of O2 gas flow rate to obtain infinite etch selectivities of blanket SiN/SiO and SiN/poly-Si than CH3F. The etch selectivity increased in both gases with the reduction of duty cycle in synchronously pulsed plasmas. Low-k spacer formation using a 60-nm gate pitch testsite was demonstrated resulting in the minimized fin recess of 4.7 nm using C4H9F-O2-He plasma at a duty cycle of 30%. This was 2.2 times smaller than that by the CH3F-He plasma. Fifty percent extended etch time resulted in a fin recess of 5.1 nm, suggesting self-limiting behavior using C4H9F-O2-He plasma chemistry. Gap structure analysis on the blanket films suggested that the selective deposition of fluorocarbon, which enhances the selectivity, is driven by plasma assisted deposition in case of the C4H9F-O2-He plasma. These unique characteristics of C4H9F can facilitate innovative plasma etch processes for nitride-based materials patterning in a wide range of applications.The performance of low-k nitride spacer etch processes for fin-field effect transistor device fabrication was investigated using C4H9F based and CH3F based plasma gas chemistries. C4H9F showed a larger process window of O2 gas flow rate to obtain infinite etch selectivities of blanket SiN/SiO and SiN/poly-Si than CH3F. The etch selectivity increased in both gases with the reduction of duty cycle in synchronously pulsed plasmas. Low-k spacer formation using a 60-nm gate pitch testsite was demonstrated resulting in the minimized fin recess of 4.7 nm using C4H9F-O2-He plasma at a duty cycle of 30%. This was 2.2 times smaller than that by the CH3F-He plasma. Fifty percent extended etch time resulted in a fin recess of 5.1 nm, suggesting self-limiting behavior using C4H9F-O2-He plasma chemistry. Gap structure analysis on the blanket films suggested that the selective deposition of fluorocarbon, which enhances the selectivity, is driven by plasma assisted deposition in case of the C4H9F-O2-He plasma. These uniq...

Deformation of the pattern or the increase in line roughness during plasma etching becomes more significant with the shrink of complementary metal–oxide–semiconductor patterns. For aggressively scaled patternings, an organic underlayer (UL) is often used under the photoresist and a thin layer of a Si-containing hardmask. In this work, the effect of ultraviolet/vacuum ultraviolet (VUV) photons on UL parameters such as wavelength, photon dose, and process order was investigated using synchrotron radiation. First, the index of refraction and extinction coefficients of mask materials such as e-beam resist [hydrogen silsesquioxane (HSQ)] and organic UL (NFC-1400; NFC) were measured by utilizing the Kramers–Kronig relations and/or ellipsometry measurements depending on the wavelength involved. Second, VUV photons at specific wavelengths, corresponding to absorption maxima of HSQ and NFC at 54 nm (HSQ), 62 nm (HSQ and NFC), 88 nm (HSQ), 112 nm (NFC), 138 nm (HSQ), 155 nm (NFC), 194 nm (NFC), and 238 nm (NFC), we...

We propose a very selective PMMA removal method from poly(styrene-block-methyl methacrylate) (PS-b-PMMA) copolymer using gas pulsing cyclic etching. Flow ratio of hydrogen (H2) added to carbon monoxide (CO) plasma was periodically changed to control etch and deposition processes on PS. By controlling the process time of each etch and deposition step, full PMMA removal including etching of the neutral layer was demonstrated at 28 nm pitch, while PS thickness remained intact. This is more than 10 times higher etch selectivity than conventional continuous plasma etch processes using standard oxygen (O2), CO–H2 and CO–O2-based chemistries.

The ability to achieve atomic layer precision is the utmost goal in the implementation of atomic layer etch technology. Carbon-based materials such as carbon nanotubes (CNTs) and graphene are single atomic layers of carbon with unique properties and, as such, represent the ultimate candidates to study the ability to process with atomic layer precision and assess impact of plasma damage to atomic layer materials. In this work, the authors use these materials to evaluate the atomic layer processing capabilities of electron beam generated plasmas. First, the authors evaluate damage to semiconducting CNTs when exposed to beam-generated plasmas and compare these results against the results using typical plasma used in semiconductor processing. The authors find that the beam generated plasma resulted in significantly lower current degradation in comparison to typical plasmas. Next, the authors evaluated the use of electron beam generated plasmas to process graphene-based devices by functionalizing graphene with...

With increasing demands on device patterning to achieve smaller critical dimensions and pitches for the 5 nm node and beyond, the need for atomic layer etching (ALE) is steadily increasing. In this work, a cyclic fluorocarbon/Ar plasma is successfully used for ALE patterning in a manufacturing scale reactor. Self-limited etching of silicon oxide is observed. The impact of various process parameters on the etch performance is established. The substrate temperature has been shown to play an especially significant role, with lower temperatures leading to higher selectivity and lower etch rates, but worse pattern fidelity. The cyclic ALE approach established with this work is shown to have great potential for small scale device patterning, showing self-limited etching, improved uniformity and resist mask performance.