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We report on the formation of shallow junctions with high activation in both n+/p and p+/n Ge junctions using ion implantation and Flash Lamp Annealing (FLA). The shallowest junction depths (Xj) formed for the n+/p and p+/n junctions were 7.6 nm and 6.1 nm with sheet resistances (Rs) of 860 ohms/sq. and 704 ohms/sq., respectively. By reducing knocked-on oxygen during ion implantation in the n+/p junctions, Rs was decreased by between 5% and 15%. The lowest Rs observed was 235 ohms/sq. with a junction depth of 21.5 nm. Hall measurements clearly revealed that knocked-on oxygen degraded phosphorus activation (carrier concentration). In the p+/n Ge junctions, we show that ion implantation damage induced high boron activation. Using this technique, Rs can be reduced from 475 ohms/sq. to 349 ohms/sq. These results indicate that the potential for forming ultra-shallow n+/p and p+/n junctions in the nanometer range in Ge devices using FLA is very high, leading to realistic monolithically-integrated Ge CMOS devices that can take us beyond Si technology.

Reduction of the contact resistance at source/drain and metal electrodes is one of the key challenges in the fabrication of high performance CMOS devices. In recent years, several studies have addressed the issue of minimizing the specific contact resistivity (ρ c ) [1] – [5] . Quite low values of ρ c in the sub-10 −9 ohm-cm 2 region have been reported for advanced technologies.

In this work, we demonstrate the possibility to achieve an ohmic contact using a low thermal budget applicable to backside processing after wafer thinning. The process window for laser annealing as a function of the thinning process is investigated. By laser melt annealing, we demonstrate the possibility for different silicide phases from pure nickel deposition on thinned 4H-SiC, formation of uniform carbon nanoclusters at the metal/SiC interface and recovery of thinning-induced defects. This has been demonstrated as a function of different thinning process and surface conditions.

We used Flash Lamp Annealing (FLA) to control dopant diffusion in the nm range in n+/p germanium junctions. The diffusion of phosphorus was slower when co-doping with fluorine at doses below 2×1014 cm−2 compared to a sample without F doping. The diffusion lengths in samples with and without F were 6.7nm and 9.1nm, respectively. In addition, precise diffusion control below 7nm could be achieved without degrading the activation level in the sample with F doping. Owing to the slow rate of diffusion, this has quite a low impact on the deactivation of P. By co-doping F with boron, diffusion in the nm range can be achieved, demonstrating the potential for controlling B diffusion in Ge. Thus, ion implantation and FLA can be usefully applied in Ge CMOS fabrication processes.

Flash Lamp Annealing (FLA) is a well-known technique for millisecond annealing. In forming ultra-shallow junctions, FLA can provide high activation levels with precise diffusion control in the nanometer range. Currently, devices with 3D structures require conformal doping as well as diffusion control. Sol-Gel Coating (SGC / Tokyo Ohka Kogyo Co., Ltd.) has a special feature, in that a very thin film on the nanometer scale can be deposited on a 3D structure. In this work, we used SGC as a dopant source and FLA to demonstrate that highly activated junctions can be formed, and effective doping can be realized. Thus, this doping technique can be applied to advanced 3D devices, such as logic, memory and CMOS image sensor.

We are developing a new flash lamp annealing (FLA) system featuring flash lamps with short duration and high output power for all CMOS technology nodes including advanced devices. With this system, we can realize lower thermal budgets and higher peak temperatures (jump temperature). Our conventional FLA tool has a wide range of annealing conditions, with annealing times from 0.8 to 100 ms. The duration of the FLA conditions of the system we are developing can be extended to deep sub-millisecond levels, making it complementary to our conventional tool. In this report, we present initial data from a new prototype system. The data clearly demonstrate that higher activation can be achieved. Notably, supersaturated activation of 4.6×1020 cm−3 can be achieved with only slight diffusion of 5.8 nm in a p+/n Si junction. In addition, Hall effect measurements revealed higher carrier concentrations of up to 1020 cm−3 in polycrystalline Si (poly-Si). These results show that the new system has the potential for forming highly activated junctions with minimal diffusion in Si and poly-Si and can contribute to the fabrication of high performance devices.

Silicon semiconductor devices have remarkably been improved by the process scaling and introduction of some boosting technologies such as high-k/metal gate and strained silicon. However further improvement is quite difficult from the view point of mobility of silicon material. To overcome this problem, an increasing amount of attention has been devoted to the investigation of some higher carrier mobility materials such as SiGe, Ge or III-V materials. Among those materials, due to higher carrier mobility of Ge, it is promising as one of the candidates for high-performance devices with low-power and high-speed operation [1]. However several challenges still remain for the fabrication of Ge MOSFETs. For junction formation, it is difficult to form shallow N+/P junction in Ge due to the anomalous high diffusion coefficient of donor ions. On the other hand, forming shallow P+/N junction is relatively easy, however the high activation is difficult. To address these problems, some processes have been proposed such as aluminum doping [2], group-III metal doping [3] and optimization of Flash Lamp Annealing (FLA) [4]. In this study, we focused on the effect of oxygen remaining in the surface region of Ge substrate. Generally, a large amount of solid-solved oxygen is contained in Ge substrate. It is known that the oxygen inside Ge crystal acts as a Thermal Double Donor (TDD) [5]. TDD will inhibit the activation of acceptor ions in Ge and result in increase in the sheet resistance (Rs) of p+ diffusion layer formed into the surface region of the Ge substrate. In order to improve the activation, the Ge substrate is pre-heated at high temperature in the vacuum chamber before ion implantation to control the oxygen concentration in the surface region. Oxygen atoms in the Ge substrate can easily out-diffuse at the initial stage of ion implantation. Furthermore implantation is carried out at relatively low temperature to avoid TED of boron. In this paper, we report the results of BF 2 implantation into Ge substrate with pre-heating process.

In recent years Solid Source Doping (SSD) has been considered as a viable option in fabricating advanced CMOS devices [1], especially for forming shallow and highly doped junctions for source drain extensions (SDE) while minimizing the damage to the devices [2]. Current scaled devices require diffusion control in the nanometer range in order to form shallow SDEs using SSD. Additionally, high doping concentrations are needed to lower the resistivity (see Fig. 1).

We demonstrated the formation of ultra-shallow n+/p junctions in Si using an arsenic-doped Sol-Gel Coating (SGC) (Tokyo Ohka Kogyo Co., Ltd.) [1] and Flash Lamp Annealing (FLA). A high arsenic dopant concentration of 1.2×1020atoms/cm3 (Xj=9.0nm, Rs= 1203ohms/sq.) with a good junction profile (2.2nm/decade) was realized with 1.4ms FLA. These results indicate that this technique can be used for conformal doping of the Source/Drain Extensions (SDE) in sub-10nm FinFETs fabricated using advanced 3D device engineering.

In this paper, we report on the formation of shallow junctions with high activation in both n+/p and p+/n Ge junctions using ion implantation and Flash Lamp Annealing (FLA). The shallowest junction depths formed for the n+/p and p+/n junctions were 9.5 nm and 10.7 nm with sheet resistances of 620 ohms/sq. and 414 ohms/sq., respectively. Additionally, by reducing knocked-on oxygen during ion implantation, the sheet resistance was decreased by 5 to 15%. The lowest sheet resistance was 235 ohms/sq. with a junction depth of 21.5 nm in the n+/p Ge. These results indicate that the potential for forming ultra-shallow n+/p and p+/n junctions in the nanometer range in Ge devices using FLA is very high, leading to realistic monolithically-integrated Ge CMOS devices.