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This article presents the s implified charge-based Enz-Krummenacher-Vittoz (EKV) [11] metal-oxide-semiconductor field-effect transistor (MOSFET) model and shows that it can be used for advanced complementary metal-oxide-semiconductor (CMOS) processes despite its very few parameters. The concept of an inversion coefficient (IC) is first introduced as an essential design parameter that replaces the overdrive voltage VG-VT0 and spans the entire range of operating points from weak via moderate to strong inversion (SI), including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40- and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation, valid from weak to SI and requiring only the VS parameter mc, is described. The normalized transconductance efficiency Gm/ID, which is a key figure-of-merit (FoM) for the design of low-power analog circuits, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to SI with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance Gds/ID follows a similar dependence with IC than the normalized Gm/ID characteristic but with different parameters accounting for drain induced barrier lowering (DIBL). The methodology for extracting the few parameters from the measured ID-VG and ID-VD characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted silicon on insulator (FDSOI) and Fin-FET 28-nm processes.

This paper investigates the phase noise in LC oscillators with NMOS cross-coupled pair by means of a linear analysis. The latter includes the impact of noise sources that are often neglected, such as gate leakage shot noise, induced gate noise and all terminal access resistances noise. Despite not considering up-conversion of flicker noise, this linear analysis still provides reliable and useful results, demonstrated by means of a detailed comparison between the analytical description and simulations results from a 40nm and a 28nm CMOS technology.

This paper carries out a power-driven performance analysis on the most widely used LC oscillators' topologies, by means of the Inversion Coefficient methodology. The aim is to investigate on the best trade-off for Internet-of-Things related applications, where power consumption shall be minimized. The analysis is based on the BSIM6 model targeting a 40nm CMOS technology to investigate the trade-offs related to each topology and comparing them with respect to output voltage amplitude, phase noise and power consumption. The comparison is based on a figure-of-merit highlighting the best biasing regions, in terms of Inversion Coefficient, for the target required performance.

This article illustrates the use of the inversion coefficient (IC) as the main design parameter to explore the various tradeoffs faced in the design of analog circuits. We start with showing that the same transconductance, gain-bandwidth (GBW) product, or input-referred thermal noise resistance of a common-source (CS) amplifier can be achieved with lower current by shifting the IC toward moderate inversion (MI) at the cost of a slight increase of the transistor aspect ratio and area. In such case the self-loading gate capacitance cannot be ignored, and accounting for it introduces a minimum bias current at an IC that lies in the middle of the MI to achieve a given GBW.