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The undoped 4-stacked Ge0.9Sn0.1 nanosheets sandwiched by double Ge0.95Sn0.05 caps without parasitic Ge channels underneath are realized by a radical-based highly selective isotropic dry etching. Highly inter-channel uniformity of the stacked GeSn nanosheets is realized by thin Ge0.9Sn0.1 (5 nm) channels and thick Ge0.95Sn0.05 caps to achieve high $\mathrm{I}_{\mathrm{\scriptscriptstyle ON}}$ . The caps are the barriers to separate the holes from the dielectrics/cap interface to reduce the surface roughness scattering. The double caps with small strain also stabilize the channels to prevent the channel buckling. The undoped GeSn nanosheets with [B] below the detection limit ( $ cm $^{-{3}}$ ) and heavily doped ( $\sim {2} \times {10}^{{21}}$ cm $^{-{3}}$ ) Ge at S/D can suppress the impurity scattering to increase the channel mobility and can reduce the S/D resistance, respectively. The high ${I}_{{\mathrm{\scriptscriptstyle ON}}} = {73}\,\,\mu \text{A}$ per stack (86 $\mu \text{A}/\mu \text{m}$ , normalized by the total perimeter of nanosheets) at ${V}_{\text {OV}} = {V}_{\text {DS}} = - {0.5}$ V is achieved for the device with the sheet width of 80 nm and the Lg of 80 nm. The quantum mechanical simulation shows that there is heavy hole population at the two ends of nanosheets.

The low contact resistivity with the median value of $3.1\times 10^{-{9}}\,\,\Omega \cdot \text {cm}^{{2}}$ (the lowest value of $1.1\times 10^{-{9}}\,\,\Omega \cdot \text {cm}^{{2}}$ ) is achieved by Ti metal contact to in-situ B-doped GeSn with B segregation at Ti/GeSn:B interface. The newly developed two-sheet-resistance model is used to extract the contact resistivity, considering the different sheet resistance of GeSn:B in the gap regions and under the metal layers. Sn incorporation into Ge lowers the Schottky barrier height of holes, and the heavy B doping at the Ti/GeSn:B interface reduces the hole tunneling distance. Fully compressively strained GeSn:B epitaxial layer with the bulk active [B] of $1.9\times 10^{{20}}$ cm−3 and [Sn] of 4.7% on the Ge-buffered Si substrate is successfully grown by chemical vapor deposition. The effects of B2H6 precursor on growth rate and [Sn] are investigated. Low contact resistivity is obtained using conventional B-doping in GeSn grown at a temperature as low as 305 °C and submitted to a post epitaxy thermal budget of 400 °C for 30 s.

An optical non-destructive method to check the existence of the parasitic Ge0.94Si0.06 channel underneath vertically stacked Ge0.91 Sn0.09 channels by infrared illumination is investigated. The 1310-nm and 1550-nm infrared light excite the electron-hole pairs in both the stacked floating channels and parasitic channel. On the other hand, the 2000-nm infrared light generates photo-excited carriers in the floating GeSn channels, but not in the parasitic GeSi channel since the photon energy is lower than the bandgap of Ge0.94 Si0.06. The main infrared responses of the floating channels and parasitic channel are the threshold voltage shift and the photocurrent, respectively. In addition, the distinct photoresponses of the stacked channels and parasitic channel are further confirmed by transistors without floating channels. The mechanisms behind the infrared responses are proposed. The existence of the parasitic channel can be detected by the infrared response for the advanced technology nodes, where the presence of the parasitic channel is not desired for performance enhancement and power reduction.

The undoped stacked GeSn channels without parasitic Ge channels are realized by a radical-based highly selective isotropic dry etching. Heavily doped Ge sacrificial layers can reduce S/D resistance and the undoped GeSn channels can increase the channel mobility. SS=89m V /dec and $\mathrm{I}_{\mathrm{O}\mathrm{N}}=42\mu 1$ per stack ( $10.5\mu A$ . per sheet) at $\mathrm{V}_{\mathrm{OV}}\mathrm{V}_{\mathrm{DS}}=-0.5\mathrm{V}$ are achieved for the undoped 4-stacked 12nm-thick nanosheets with 120nm gate length and the width larger than 50nm. The etching selectivity and the channel uniformity are highly improved by the dry etching as compared to H202 wet etching. Both dry etching and undoped channel are essential to obtain stacked wide nanosheets with high performance.

Fully compressively strained GeSn quantum-well channels sandwiched by Ge sacrificial layers on 200-mm silicon-on-insulator (SOI) wafers are grown using chemical vapor deposition. The transmission electron microscopy images indicate that dislocations are confined near the relaxed Ge buffer/SOI interface, resulting in low defect densities in the stacked GeSn channels. The top Ge cap is essential to ensure that the top GeSn channel matches the other two channels during the Ge etching. Channel release is obtained by etching of the Ge sacrificial layers with optimum ultrasonic-assisted H2O2. The low thermal budget gate-stack (400 °C) and S/D parasitic resistance reduction are achieved. The first stacked 3-Ge0.93Sn0.07-channel p-gate-all-around FET with ${L} _{\text {CH}}= 60$ nm has a record high ${I}_{ \mathrm{\scriptscriptstyle ON}}=1975~\mu \text{A}/\mu \text{m}$ (per channel width) at ${V}_{\text {OV}}={V}_{\text {DS}}=-1$ V, among all GeSn pFETs. The junctionless device structure is used to simplify the process.

Although the Sn content in GeSn can reach 10% using chemical vapor deposition, the reduction of Sn content by in-situ boron doping and solid phase doping by chemical vapor deposition are observed. The Sn loss increases with the increasing boron concentration in GeSn:B alloys, while there is no Sn reduction at the similar phosphorus doping level in GeSn:P. Based on the first principle calculations, the energy for boron to place Sn in GeSn is lower than that for boron to place Ge, indicating that boron atoms prefer to occupy Sn sites. The Sn loss is more serious for boron-implanted GeSn with thermal annealing at 400 °C than in-situ boron-doped GeSn even with 500 °C thermal annealing.

Although the melting laser annealing can activate the heavily phosphorus-doped epitaxial Ge on silicon-on-insulator by chemical vapor deposition, the dopant segregation occurs after the rapid thermal process at 550 °C for 3 min even with SiO2 capping. However, the active dopant concentration can be recovered after the second laser annealing to melt Ge again due to higher P solubility in the liquid Ge than the solid Ge. The temperature distribution and the melt depth of epi-Ge is mainly determined by the laser fluence. Selective laser annealing is used to simultaneously reach low dopant concentration in the channel regions for good gate controllability, and high concentration in the source and drain regions with low parasitic resistance for the transistors. As a result, the low specific contact resistivity of $1.2\ \times \,\,10^{-8}\,\,\Omega $ cm2 using the Ni–Ge/n+Ge, the 21% current enhancement of the Ge + Si nFET as compared to the device without the selectively second laser annealing and the Ni–Ge contact, and the similar subthreshold slope after the selectively second laser annealing are achieved. The Si channel underneath the Ge channel also contributes about 38% of the total current.

Si incorporation as small as 2% into Ge can achieve sufficient etching selectivity of heavily phosphorus- doped Ge sacrificial layers over unintentionally doped Ge 0.98 Si 0.02 to form two stacked Ge 0.98 Si 0.02 nanowire channels, and introduce 0.27% uniaxial tensile strain for the electron mobility enhancement. The alloy scattering is still minimal for 2% Si. The parasitic Ge/Si channel underneath the Ge 0.98 Si 0.02 channels is completely removed by optimized etching. The infrared response of the parasitic channel is a non-destructive method to further confirm the removal of the parasitic channel. VT can be tuned by PMA, and ION can be enhanced by short L G . Record ION of 48 μA at V OV =V DS =0.5V and record Q (G m,max/ SS SAT ) of 8.3 at V DS =0.5V with L G = 40 nm are achieved among Ge nFETs. The results are comparable to Si nFETs.

The tensily strained high Ge content (85%) GeSi multi-channels stacked on the Si channel with channel size optimization have good subthreshold behaviors (SS, DIBL, and $\mathrm{I}_{\mathrm{off}}$ ), and meanwhile maintain high $\mathrm{I}_{\mathrm{on}}$ . By narrowing GeSi channel, the bandgap of the GeSi can be increased by quantum confinement and the short channel effect can be suppressed. This also causes the more positive $\mathrm{v}_{\mathrm{t}}$ for GeSi than Si. As a result, $\mathrm{SS}=76\mathrm{mV}/\mathrm{dec}, \mathrm{DIBL}=36\ \mathrm{mV}/\mathrm{V}$ can be achieved due to the benefit of superior subthreshold behaviors of the Si channel underneath. The $\mathrm{I}_{\mathrm{on}}/\mathrm{I}_{\mathrm{off}}$ is improves to be 1.2E7. The high $\mathrm{I}_{\mathrm{on}}=44\mu \mathrm{A}$ perstack at $\mathrm{Vov}= \mathrm{V}_{\mathrm{DS}}=1\mathrm{V}$ , is contributed from both the GeSi and Si channels, and it is further enhanced to $46\ \mu \mathrm{A}$ by the external strain. The relatively low flicker noise indicates that the novel structure can mitigate the reliability issue of GeSi channels by the highly reliable Si channel underneath.

In this article we provide a comparative and systematic study on contact formation for germanium-tin (GeSn) thin films containing a high percentage of Sn (8 at.%). 20 nm of Nickel (Ni), Titanium (Ti), or Platinum (Pt) was deposited on Ge0.92Sn0.08 layers grown on Ge substrates, and subsequently annealed between 300 and 500 °C to form stanogermanide alloys. Several experimental techniques were employed to characterize the material and the electrical contact behaviour, with the purpose of identifying the most promising stanogermanide contact candidate, in terms of low sheet resistance, low surface roughness and low formation temperature. Among these three different metals we found that, for nanoelectronic applications, nickel-stanogermanide (NiGeSn) was the most promising candidate based on a low sheet resistance combined with a low formation temperature, below 400 °C. PtGeSn showed better behaviour in terms of thermal stability compared with the other two options, while Ti was found to be relatively unreactive under these annealing conditions, resulting in poor TiGeSn formation. For the lowest resistance stanogermanide contact generated, namely NiGeSn formed at 300 °C, detailed lattice resolution Transmission Electron Microscopy imaging, combined with fast Fourier transformation analysis, identified the formation of the Nix-1(GeSn)y-1 phase.

It is the first time that CVD-grown GeSn channels with low thermal budget of 400°C significantly outperforms the Ge channel processed at high thermal budget of 550°C. Low thermal budget is necessary to prevent the Sn loss during the process. Note that only MBE-grown GeSn had large mobility reportedly in the past. Even with high Sn content (9%), the strong photoluminescence is observed from GeSn layers on Ge buffer on 300mm Si (001), indicating the high crystalline quality by CVD epitaxy. Ge cap with significant Δ Ev at Ge/GeSn interface can ensure the gate stack quality, and reduce the scattering of holes in the GeSn quantum wells by oxide/interface charges and surface roughness. However, the mobility is degraded by thick cap due to low hole population in the GeSn wells. The ∼7% mobility enhancement on channel direction is observed using external transverse uniaxial tensile strain of ∼0.11% due to the reduction of effective mass. The mobility of GeSn QW p-MOSFETs increases with decreasing temperature at both high and low inversion carrier density, indicating that the mobility is dominated by phonon scattering. On the contrary, Ge channels are dominated by Coulomb scattering at low inversion carrier density, which has decreasing mobility with decreasing temperature. The normalized noise power density of GeSn p-MOSFETs decreases with increasing Ge cap thickness, reportedly for the first time, indicating that the carrier number fluctuation and correlated mobility fluctuation can be reduced when the carriers are away from interface.

The low channel doping concentrations of 1.2×1019 cm−3 to deplete the channel and the high S/D doping of 1.2×1020 cm−3 to reduce the S/D resistance are achieved simultaneously by selective laser annealing on the same CVD P-doped epi-Ge on SOI without ion implantation. The device with Wfin down to 7 nm, EOT = 2.2 nm, and Lch = 60 nm has Ion = 1146 μA/pm, Ion/Ioff = 2×106, and SS = 95 mV/dec. The Ion can be further boost to 1235 μA/μm with external uniaxial tensile strain of 0.16%. The self-heating effect is responsible in part for such high Ion, because the high device temperature can reduce the dominant impurity scattering in the channel. The increasing mobility with increasing temperature indicates the impurity scattering is dominant. The lower low frequency noise is observed with junctionless (JL) gate-all-around (GAA) FETs than planar inversion mode (INV) devices due to the bulk conduction nature of JL FETs.

Pseudomorphic Ge 0.91 Sn 0.09 on Ge on Si with strong photoluminescence and low defect density is used for p-MOSFET channels. The mobility of Ge 0.91 Sn 0.09 Quantum Well p-MOSFETs are higher than control Ge p-MOSFETs due to hole population in the GeSn wells. The 7.5% mobility enhancement on channel direction is observed using external transverse uniaxial tensile strain (∼0.11%). The highest [Sn] of 9% in the channels grown by CVD, Pt SB S/D, high I on /I off ratio, and strain-enhanced mobility are obtained in this work.

The electron concentration of 3×1020 cm−3 in phosphorus-doped Ge is obtained by in-situ chemical vapor deposition doping and laser annealing. The laser annealing effectively improve the crystallinity in the Ge layer. The pulse laser not only activates the phosphorus, but also produces the biaxial tensile strain. With the nickel germanide contact, the contact resistivity is as low as 1.5×10−8 Ω-cm2 by greatly reducing the tunneling distance. The misfit dislocations at the Ge/Si interface lead to the ideality factor of 1.6 for the Ge/Si hetero-junction diode with on/off ratio of ∼1×105.

A Ge/GeSn/Ge single quantum well with 5% Sn content was grown by chemical vapor deposition on a Si substrate using Ge2H6 and SnCl4 precursors. External biaxial tensile strain was mechanically applied to the Ge/Ge0.95Sn0.05/Ge quantum well for the photoluminescence measurement. Note that the Ge0.95Sn0.05 layer is still under compressive strain due to the large internal compressive strain of the GeSn, although the external bending produces the tensile strain. The direct emission of tensily strained Ge buffer shifts toward lower energy, while the direct emission of pseudomorphic Ge0.95Sn0.05 quantum well does not have significant shift. The strain-induced energy changes of heavy holes and light holes in the Γ valley are extracted by fitting the photoluminescence spectra. Based on the nonlocal empirical pseudopotential method and the model-solid theory, a type-I band alignment is used for the fitting of photoluminescence spectra. The experimentally extracted band edge shifts from the photoluminescence measurement have good agreement with theoretical calculation.