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This paper investigates the p-Ge/Al2O3/ZrO2/TiN gate stacks that were subjected to different slot plane antenna oxidation (SPAO) conditions: 1) prior to any high-k atomic layer deposition (ALD); 2) in between Al2O3 and ZrO2ALD layers; and 3) after the ALD of high- ${k}$ layers. The carrier transport mechanisms as a function of temperature on these samples were observed to be different. The SPAO treatment effectively removes the trap centers in ZrO2 and Al2O3 layers depending on the SPAO treatments. Fowler-Nordheim tunneling seems to be the dominant transport mechanism at high field range when SPAO was performed after the high- ${k}$ layers were deposited. On the other hand, Poole-Frenkel emission and hopping conduction mechanism are dominant for other two samples in both gate electron injection and substrate electron injection (SEI) modes. The trap center ( $ {\phi }_{\text{t1}} = {0.13}$ eV) remains in the ZrO2 when ZrO2 is not subjected to the SPAO. Trap energy level $ {\phi }_{\text{t1}}$ (0.13 eV) was removed and $ {\phi }_{\text{t2}}$ (0.27 eV) still exists when only Al2O3 oxide layer was exposed to SPAO. Hopping distance, ${a}$ (about 0.3 nm) is extracted by hopping conduction model. After time dependent dielectric breakdown measurement, it was found that if GeO2 exists at the interface then it can be degraded easily by SEI stress. On the other hand, if SPAO was processed in between the high- ${k}$ layers the formation of a GeOx layer enhances the interface quality and provides better immunity to degradation under stress.

Multi-patterning processes such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) present new challenges to the semiconductor device manufacturing such as increased relative cost to previous nodes, longer cycle times, and increased (local) edge placement error between grid and cut/block layers. As the scaling requirements continue, the factors driving both EPE and electrical yield such as overlay, critical dimension control (CDU) and stochastics (LCDU) become greater concerns to multi-patterning. In addition to lithographic process variations, the unit processes such as plasma/vapor etch, deposition, wet/cleans can contributes additional variation in spacer/mandrel profiles leading to poor CDU control and ultimately within-wafer pitch walking. In this paper, we outline alternative SAQP integration schemes to improve the feature profile of both mandrel and spacer to minimize process variability. This patterning scheme designated as fly-cut SAQP introduces new concepts such top spacer removal by chemical-mechanical planarization, mandrel foot mitigation layers, multi-layered mandrel for accurate polish end-point and void-free gap fill to realize high fidelity transfer to the underlying hardmask. Finally, we will demonstrate the effectiveness for this new integration scheme as a candidate for multi-color/self-aligned block (SAB) and highlight the additional benefits of using such an approach.

For exploring the prospect of higher-k dielectric phase engineering on a high mobility substrate, films of Hf1-xZrxO2 with varying x-values (0 ≤ x ≤ 1) were deposited on Al2O3 passivated Ge substrates using atomic layer deposition (ALD) with a cyclic deposit-anneal-deposit-anneal (DADA) scheme. The evolution of monoclinic to higher-k tetragonal structure with increasing ZrO2 concentration was probed by grazing incident x-ray diffraction and partial reciprocal space maps using the highly brilliant synchrotron x-ray source at the Cornell High Energy Synchrotron Source (CHESS). A primarily amorphous/nano-crystalline matrix of the as-deposited films changed to randomly aligned grains of nanocry stalline MO2 (M=Hf, Zr) after post deposition annealing at 800 °C for 200 seconds. In contrast, the DADA films annealed for same thermal budget showed high degree of preferred orientation along certain crystallographic directions. With increasing ZrO2 content, the structure of the films changed from a monoclinic to a tetragonal phase. A lower amount of ZrO2 (x = 0.33) was required for stabilizing the tetragonal phase in films grown on Al2O3 passivated Ge substrate as compared to similar films grown on a Si substrate via the same DADA process (x ≥ 0.50).

Even through Ge/high-k interface has been extensively studied the high leakage current associated with these gate stacks continues to introduce frequency dispersion and hysteresis in capacitance-voltage (CV) and conductance-voltage (GV) characteristics. These dispersions severely limit the understanding the interface and accurate estimation of interface state density, Dit and equivalent oxide thickness (EOT). Since several parameters like EOT, flatband voltage, bulk doping, surface potential as a function of gate voltage are important and bulk defect and interface defect concentration affect the CV and GV characteristics several corrections to the characteristics are required to obtain accurate values. We have measured the CV and GV characteristics of Ge/ALD 1nm-Al2O3/ALD 3.5nm-ZrO2/ALD TiN MOS capacitors with three different interface treatments by HP4284 LCR meter using different frequencies. The interface treatments are (i) simple chemical oxidation (Chemox); (ii) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR&SPAOx); and (iii) COR followed by vapor O3 treatment (COR&O3). The plots were corrected by three different methods. Firstly, we removed the effect of sheet resistance, RS . The second approach uses data (capacitance and conductance) measured at two different frequencies to solve two unknown variables (capacitance and conductance) (1). The solved CV plot is closer to the corrected CV plot at 1 MHz rather than that at 100 KHz. This allows us to use 1MHz corrected data to obtain the EOT information. Additionally, this approach helps to verify that 1MHz data is robust assuming that defects do not respond to the other frequencies used here. The third approach is to modify the measurement circuits (2) to enhance CV and GV characteristics. Fig. 1 shows the CV characteristics after the corrections by three different approaches for three different samples. COR&SPAOx samples show excellent CV characteristics. The details of all the correction methods and the advantages of these methods to correct CV and GV will be discussed. We will demonstrate that the correction methods are suitable for accurately measure the interface characteristics. The Dit calculated by two method (conductance and capacitance spectroscopy) (Fig. 2) are compared and discrepancy of the results between different samples and different methods will be explained. References Y. Ding and D. Misra, J. Vac. Sci. Technol. B, 33, 021203, 2015. K.J. Yang and C. Hu, IEEE Trans on Electron Dev, 46(7), 1500, 1999. K.S.K Kwa, S. Chattopadhyay, N.D. Jankovic, S.H. Olsen, L.S. Driscoll, and A.G. O'Neill, Semicond. Sci. Technol., 18(2), 82, 2003. Figure 1

We have integrated ALD barrier and Ru liner for novel interconnect integration and have evaluated electrical properties and time dependent dielectric breakdown (TDDB). RC and via resistance were reduced by the ALD barrier, and particularly it was confirmed that TDDB performance can be improved by using ALD TaAlN with an ultrathin film. Accordingly, ALD TaAlN barrier and CVD Ru liner are attractive barrier/liner combination for next generation interconnect integration schemes.

Resistance capacitance time delay in Cu interconnects is becoming a significant factor requiring further performance improvements in future nanoelectronic devices. Choice of alternate interconnect materials, for example, refractory metals, and subsequent integration with underlying barrier and liner layers are extremely challenging for the sub-10 nm nodes. The development of conformal deposition processes for alternate interconnects, liner, and barrier materials are crucial in order for implementation of a possible replacement for Cu interconnects for narrow line widths. In this study, the authors report on ultrathin (∼3 nm) chemical vapor deposition (CVD) grown ruthenium films on 0.5 and 1 nm thick metal nitride (TiN, TaN) barrier layers deposited via atomic layer deposition (ALD). Using scanning electron microscopy, the authors determined the effect of the underlying barrier layer on the coverage of the ruthenium overlayer. The authors utilized synchrotron x-ray diffraction with in situ rapid thermal an...

Using a five-step atomic layer deposition (ALD)-anneal (DADA) process, with 20 ALD cycles of metalorganic precursors followed by 40 s of rapid thermal annealing at 1073 K, we have developed highly crystalline Hf1−xZrxO2 (0 ≤ x ≤ 1) thin films (

In this study, the authors investigated atomic layer deposition (ALD) of B2O3 and BN for conformal, ultrashallow B doping applications and compared the effect of dopant-containing overlayers on sheet resistance (Rs) and B profiles for both types of films subjected to a drive-in thermal anneal. For the deposition of B2O3, tris(dimethylamido)borane and O3 were used as coreactants and for the deposition of BN, BCl3 and NH3 were used as coreactants. Due to the extreme air instability of B2O3 films, physical analysis was performed on B2O3 films, which were capped in-situ with ∼30 A ALD grown Al2O3 layers. For the BN films, in-situ ALD grown Si3N4 capping layers (∼30 A) were used for comparison. From spectroscopic ellipsometry, a thickness decrease was observed after 1000 °C, 30 s anneal for the B2O3 containing stack with 60 ALD cycles of B2O3, whereas the BN containing stacks showed negligible thickness decrease after the annealing step, regardless of the number of BN cycles tested. The postanneal reduction in...

This work investigates the interface state density, Dit by conductance method for two different processing conditions: (1) cyclic deposition and slot-plane-antenna (SPA) Ar plasma exposure, DSDS, and (2) cyclic deposition and annealing, DADA, during the deposition of ALD Hf1-xZrxO2 to fabricate the TiN/Hf1-xZrxO2/SiON/Si gate stack. The Zr percentage was varied in the dielectrics from x = 0 to 0.31 and 0.8 for DSDS processing and x = 0 to 0.8 for DADA processing. The control samples were deposited with standard atomic layer deposition (ALD) process (As-Dep) without any cyclic treatment. The addition of ZrO2 and SPA plasma exposure is found to suppress interface state generation. DSDS Hf1-xZrxO2 with x = 0.8 demonstrated superior equivalent oxide thickness downscaling and the lowest Dit. The electron affinity variation of Hf and Zr ion seems to contribute to reduced Dit generation after a constant voltage stress. On the other hand, DADA process increases the midgap Dit when Zr is added to HfO2. In addition...