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Although the melting laser annealing can activate the heavily phosphorus-doped epitaxial Ge on silicon-on-insulator by chemical vapor deposition, the dopant segregation occurs after the rapid thermal process at 550 °C for 3 min even with SiO2 capping. However, the active dopant concentration can be recovered after the second laser annealing to melt Ge again due to higher P solubility in the liquid Ge than the solid Ge. The temperature distribution and the melt depth of epi-Ge is mainly determined by the laser fluence. Selective laser annealing is used to simultaneously reach low dopant concentration in the channel regions for good gate controllability, and high concentration in the source and drain regions with low parasitic resistance for the transistors. As a result, the low specific contact resistivity of $1.2\ \times \,\,10^{-8}\,\,\Omega $ cm2 using the Ni–Ge/n+Ge, the 21% current enhancement of the Ge + Si nFET as compared to the device without the selectively second laser annealing and the Ni–Ge contact, and the similar subthreshold slope after the selectively second laser annealing are achieved. The Si channel underneath the Ge channel also contributes about 38% of the total current.

The low channel doping concentrations of 1.2×1019 cm−3 to deplete the channel and the high S/D doping of 1.2×1020 cm−3 to reduce the S/D resistance are achieved simultaneously by selective laser annealing on the same CVD P-doped epi-Ge on SOI without ion implantation. The device with Wfin down to 7 nm, EOT = 2.2 nm, and Lch = 60 nm has Ion = 1146 μA/pm, Ion/Ioff = 2×106, and SS = 95 mV/dec. The Ion can be further boost to 1235 μA/μm with external uniaxial tensile strain of 0.16%. The self-heating effect is responsible in part for such high Ion, because the high device temperature can reduce the dominant impurity scattering in the channel. The increasing mobility with increasing temperature indicates the impurity scattering is dominant. The lower low frequency noise is observed with junctionless (JL) gate-all-around (GAA) FETs than planar inversion mode (INV) devices due to the bulk conduction nature of JL FETs.

Al2O3/TiO2 stack layers deposited by the plasma-enhanced atomic layer deposition enhance photoluminescence intensity by reducing effective surface recombination velocities on both n-type and p-type monocrystalline Si. The field effect of negative oxide charges in the dielectrics is responsible for the low effective surface recombination velocity. The dependence of the effective surface recombination velocity on the photoluminescence intensity is investigated by the 2D numerical simulation. The bilayer stacks without texture also reduce the AM1.5-weighted front side reflectance to 11.8%. The field-effect passivation of Al2O3/TiO2 films is further improved by a forming gas annealing due to the additional increase of the negative oxide charge density.