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The fabrication of a 2.5D glass interposer was demonstrated, and its electrical performance, including signal transmission, was characterized. Single-sided multi-level enhanced copper redistribution layers were fabricated on a glass substrate with through glass via. This structure will enable heterogeneous chip integration requiring both high-speed signal processing and high-density signal lines. The 3D-simulated insertion loss (Sdd21) of the high-speed signal lines (5 mm in length), which were fabricated using a semi-additive process, was as low as −0.86 dB at a frequency of 16 GHz due to low conductor loss. The insertion loss was 1/12 that of a damascene-based signal line. The 4-μm-pitch Cu traces used as high-density signal lines were electrically isolated by using optimized barrier metal etching chemistry. The lower insertion loss and reliable electrical isolation make this interposer advantageous compared to competitive packaging technologies such as 2.5D silicon and 2.1D organic interposers.

Downsizing the Cu signal traces in the redistribution layer is an effective approach to increasing the number of signal I/O lines and thereby greatly increasing signal processing performance between logic and memory chips in advanced fine-pitch packaging. Downsized Cu traces, however, are vulnerable to current stress, which degrades electromigration resistance. This is a serious problem in advanced fine-pitch packaging. In a conventional redistribution layer, the Cu traces are completely covered with an organic dielectric. Weak adhesion force between the traces and the dielectric accelerates electromigration, in addition to causing current stress. Thus, interfacial modification of the Cu traces is critical to enhancing electromigration resistance. In this report, we introduce a new type of redistribution layer structure in which the Cu traces are completely covered with inorganic dielectrics. This structure increases electromigration resistance as much as 10,000 times that of Cu traces in a conventional redistribution layer.

Aggressive scaling down of the Cu trace pitch in the redistribution layer (RDL) is needed to meet the design rule for high-density I/O used in advanced packaging. Such a downsized RDL, however, will be vulnerable to voltage and current stresses, in addition to environmental stress. Voltage stress, for example, degrades the reliability of electrical isolation (dielectric strength). This will likely be a serious problem when the pitch of the Cu traces becomes less than 4 µm since Cu migration will become substantial due to a rapid increase in the electric field between traces. This means that the conventional RDL structure based on a semi-additive process may fail to meet the performance specified by the Joint Electron Device Engineering Council (JEDEC) reliability standard. A previously proposed enhanced RDL, in which the Cu traces are covered with two types of inorganic dielectrics, showed potential performance suitable for advanced packaging technologies in terms of both electrical and mechanical reliability. The Cu trace pitch has now been scaled down from 20 µm to as small as 2 µm. Characterization of this downsized redistribution layer in terms of electrical reliability using biased highly accelerated temperature and humidity stress testing and electromigration testing showed that the first inorganic dielectric completely suppressed Cu migration and Cu surface diffusion, which degrade electrical isolation and electromigration resistance, respectively. This downsized enhanced RDL is thus promising for advanced high-density fan-out wafer-level packaging and 2.5 D interposer packaging.

An enhanced redistribution layer architecture has been developed in which the Cu wires are directly covered with a double layer consisting of two types of dielectrics by using a semi-additive process. The double layer enhanced the thermal and electrical reliabilities of the Cu wires. Moreover, it enabled fabrication of a single-sided nine-level redistribution layer embedded with a fully stacked via. This greatly increased wiring layout flexibility and enhanced the transmission rate. Characterization of this architecture revealed that it has several advantages for advanced packaging technologies including a 2.5D interposer.