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In this study, the correlation between the Emission Microscopy (Em.Mi.) related to the failure site of the 4H-SiC 650V MOSFET devices after reliability test and epitaxial dislocation defects is presented. Devices failed at the High-Temperature Reverse Bias (HTRB) test were considered. Device layers have been stripped out by chemical wet etching and etched in a high temperature KOH solution to characterize defects emerging at the SiC surface. This approach was used to correlate failure emission spots with underlying structure of the material. KOH etching process on delayered devices was performed at 500°C for 10 minutes and then analysis by optical microscopy and SEM was carried out for defect classification and correlation with failure location.

In this work, the origin of the dielectric breakdown of 4H-SiC power MOSFETs was studied at the nanoscale, analyzing devices that failed after extremely long (three months) of high temperature reverse bias (HTRB) stress. A one-to-one correspondence between the location of the breakdown event and a threading dislocation propagating through the epitaxial layer was found. Scanning probe microscopy (SPM) revealed the conductive nature of the threading dislocation and a local modification of the minority carriers concentration. Basing on these results, the role of the threading dislocation on the failure of 4H-SiC MOSFETs could be clarified.

In this paper, a two-dimensional (2D) planar scanning capacitance microscopy (SCM) method is used to visualize with a high spatial resolution the channel region of large-area 4H-SiC power MOSFETs and estimate the homogeneity of the channel length over the whole device perimeter. The method enabled visualizing the fluctuations of the channel geometry occurring under different processing conditions. Moreover, the impact of the ion implantation parameters on the channel could be elucidated.

In this work, the breakdown of 4H-SiC MOSFETs was correlated with the presence of different crystalline defects in the 4H-SiC epitaxial layer. First, in a wafer level characterization, the devices not working at t = 0 s showed the presence of down-falls and were discarded. Then, the Fowler-Nordheim (FN) gate bias conduction was used to screen the remaining packaged MOSFETs. In particular, the devices failing under high temperature gate bias (HTGB) stress exhibited an anomalous FN behavior and the presence of a surface bump. Finally, a threading dislocation (TD) was systematically found at the breakdown location during high temperature reverse bias (HTRB) stress. Scanning probe microscopy (SPM) techniques revealed the increase of the minority carrier concentration close to the defect up to 13 orders of magnitude larger than in the ideal 4H-SiC epitaxial layer. In this way, the key role of the TD in the dielectric breakdown of 4H-SiC MOSFET was unambiguously demonstrated.

In this paper the defects generated by ion implantation in 4H-SiC DIMOSFET (Double Implanted MOSFETs), and their evolution after annealing process, have been studied in detail. The point defects generated by the source or body implantation process have been detected by micro-photoluminescence (µPL) and the effect of these defects on the electrical characteristics of the DIMOSFET has been studied. The role of the annealing process has been carefully investigated by using different temperatures. It appears fundamental for the restoring of the crystal damage. The effect of the ion implantation dose has been investigated as well. By reducing the source ion implanted dose a large decrease of point defects has been detected and a considerable improvement of the electrical characteristic of the DIMOSFET has been observed.

In this paper the influence of point defects generated by the ion implantation process in 4H-SiC DIMOSFET has been studied in detail. The point defects generated by the source or body implantation process have been detected by micro-photoluminescence and the effect of these defects on the electrical characteristics of the DIMOSFET has been studied. In particular it has been observed that a reduction of the source ion implanted dose produces a large reduction of point defects in the source region and a considerable improvement of the electrical characteristic of the DIMOSFET.

The dynamic response of a MEMS accelerometer can be influenced by several multi-physics effects, especially if the gaps between the shuttle and the stator attain sub-micrometric values. The present paper aims at tackling the aforementioned issues by means of a suitable experimental procedure, which has been purposely devised for the problem at hand, and through the execution of numerical analyses (based on the Finite Element Model). The effect of parasitic electrostatic forces and hydrodynamic forces is clearly demonstrated.

The origin of dielectric breakdown was studied on 4H-SiC MOSFETs that failed after three months of high temperature reverse bias (HTRB) stress. A local inspection of the failed devices demonstrated the presence of a threading dislocation (TD) at the breakdown location. The nanoscale origin of the dielectric breakdown was highlighted with advanced high-spatial-resolution scanning probe microscopy (SPM) techniques. In particular, SPM revealed the conductive nature of the TD and a local increase of the minority carrier concentration close to the defect. Numerical simulations estimated a hole concentration 13 orders of magnitude larger than in the ideal 4H-SiC crystal. The hole injection in specific regions of the device explained the failure of the gate oxide under stress. In this way, the key role of the TD in the dielectric breakdown of 4H-SiC MOSFET was unambiguously demonstrated.