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Your search keyword '"ATMEL [Rousset]"' showing total 7 results
Start Over Author "ATMEL [Rousset]" Topic 01 natural sciences
7 results on '"ATMEL [Rousset]"'

1. An Ultra-Low Power and High Performance Single Ended Sense Amplifier for Low Voltage Flash Memories

Author

Hassen Aziza, Julien Mellier, W Steve Ngueya, Jean-Michel Portal, Stephane Ricard, Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP), Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS), StarChip (StarChip), ATMEL [Rousset], and Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)-Aix Marseille Université (AMU)

Subjects
010302 applied physics, Ultra low power, 060102 archaeology, Computer science, business.industry, Sense amplifier, Electrical engineering, 06 humanities and the arts, 01 natural sciences, Flash (photography), 0103 physical sciences, 0601 history and archaeology, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Low voltage, ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2018
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2. Power efficiency optimization of charge pumps in embedded low voltage NOR flash memory

Author

Julien Mellier, Stephane Ricard, Jean-Michel Portal, W Steve Ngueya, Hassen Aziza, Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP), Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)-Aix Marseille Université (AMU), StarChip (StarChip), ATMEL [Rousset], and Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Computer science, business.industry, 020208 electrical & electronic engineering, Electrical engineering, Charge (physics), 02 engineering and technology, Elementary charge, 7. Clean energy, 01 natural sciences, Flash memory, Power (physics), Memory cell, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Charge pump, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Low voltage, Electrical efficiency, ComputingMilieux_MISCELLANEOUS
Abstract

A new concept for improving efficiency of a charge pump system is presented. The concept is based on a set of elementary charge pumps connected in parallel in addition to the detection of the number of memory cells to be programmed at the same time. The proposed solution is able to supply current to a memory cell, while operating with maximum efficiency by activating one, two or more charge pumps. The proposed system is implemented using a 55 nm UMC High Voltage CMOS technology with a power supply of 1.2V. In the worst case where only one cell is to be programmed, simulation results show an improvement of power efficiency by a factor 2. The area penalty of the proposed system is only 3.8%.

Published
2017
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3. Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

Author

Gaëtan Toulon, Bruno Villard, David Flores, I. Cortes, Frédéric Morancho, Elsa Hugonnard-Bruyère, Centro Nacional de Microelectronica [Spain] (CNM), Équipe Intégration de Systèmes de Gestion de l'Énergie (LAAS-ISGE), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), ATMEL [Rousset], MEDEA +, SPOT-2 (ATMEL / LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées

Subjects
Engineering, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, NBL, 01 natural sciences, PMOS logic, law.invention, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Materials Chemistry, Electronic engineering, Electrical and Electronic Engineering, Thin film, 010302 applied physics, TCAD, business.industry, CMOS, Transistor, RESURF, P-channel, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Variable bitrate, LDMOS, [SPI.TRON]Engineering Sciences [physics]/Electronics, Electronic, Optical and Magnetic Materials, Power (physics), Optoelectronics, 0210 nano-technology, business, Layer (electronics), Thin-SOI technology, Voltage
Abstract

International audience; This paper analyses the experimental results of voltage capability (VBR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

Published
2012
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4. Design techniques for EEPROMs embedded in portable systems on chips

Author

M. Merandat, C. Papaix, G. Medulla, J. Guichaoua, J.M. Daga, S. Ricard, D. Auvergne, ATMEL [Rousset], Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Atmel Corporation (ATMEL), ATMEL, Conception et Test de Systèmes MICroélectroniques (SysMIC), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
010302 applied physics, Engineering, Boosting (machine learning), business.industry, 020208 electrical & electronic engineering, 02 engineering and technology, Energy consumption, Ring oscillator, 01 natural sciences, Hardware and Architecture, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, System on a chip, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, EPROM, business, Software, Access time, Logic programming, Computer hardware, Voltage
Abstract

International audience; These design techniques target EEPROMs embedded in portable, battery-powered devices that operate under a wide supply voltage range. A current-controlled ring oscillator provides stable programming pulse generation, optimizing write time. Logic delay optimization and a word line boosting technique decrease read access time.

Published
2003
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5. Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells

Author

R. Gaillard, N. Renaud, S. Benhammadi, Guillaume Hubert, T. Carriere, C. Weulerse, Frédéric Wrobel, Lorena Anghel, C. Rusu, Antonin Bougerol, N. Buard, EADS, Corporate Research Center, EADS Paris, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), ATMEL [Rousset], LPES - Laboratoire de Physique Electronique des Solides, EA 1174, Université Nice Sophia Antipolis (... - 2019) (UNS), Université Côte d'Azur (UCA)-Université Côte d'Azur (UCA), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), and COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)

Subjects
010302 applied physics, Nuclear reaction, Engineering, CMOS-realization, 010308 nuclear & particles physics, business.industry, Spice, Logic simulation, Electrical engineering, NAND gate, 01 natural sciences, CMOS, Application-specific integrated circuit, PACS 85.42, 0103 physical sciences, Electronic engineering, Neutron, Transient (oscillation), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract

International audience; This paper presents a methodology for analyzing the behavior of nanometer technologies regarding "Multiple Event Transients" (MET) caused by nuclear reaction induced by atmospheric neutrons. For the first time, currents collected by several sensitive areas of an ASIC cell resulting from a nuclear reaction are addressed by simulation. Libraries of several thousand types of currents are obtained for neutron energy range between 1 and 200 MeV. Group of currents are simultaneously injected at SPICE level and their effects are monitored on the cell output. Following an amplitude criterion, output transient duration and associated occurrence probability are recorded. A 130nm NAND gate from ATMEL Corporation is first used to illustrate the methodology and a comparison between Single Event Transients and Multiple Event Transients effects is presented. Finally, results regarding five different combinational cells in the ATMEL 130nm library are presented and discussed.

Published
2007
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6. Interconnect Capacitance Modelling in a VDSM CMOS Technology

Author

David Bernard, Pascal Nouet, Christian Landrault, ATMEL [Rousset], Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
010302 applied physics, Interconnection, Silicon, Computer science, chemistry.chemical_element, 02 engineering and technology, 01 natural sciences, Capacitance, 020202 computer hardware & architecture, Set (abstract data type), Layout extraction, CMOS, chemistry, 0103 physical sciences, Lookup table, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; This paper introduces a set of analytical formulations for 3D modelling of inter- and intra-layer capacitance. Based on real silicon data, we have developed and validated efficient and accurate analytical models that are an helpful alternative to lookup tables or numerical simulations.

Published
2002
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7. Ultrahigh frequency DC-to-DC converters using GaAs power switches

Author

G. Salmer, S. Ajram, Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), and ATMEL [Rousset]

Subjects
Silicon, Materials science, 02 engineering and technology, High-electron-mobility transistor, Frequency conversion, 01 natural sciences, 7. Clean energy, [SPI]Engineering Sciences [physics], Gallium arsenide, MOSFET circuits, 0103 physical sciences, MOSFET, 0202 electrical engineering, electronic engineering, information engineering, Prototypes, Electrical and Electronic Engineering, Power MOSFET, 010302 applied physics, HEMTs, business.industry, 020208 electrical & electronic engineering, Bipolar junction transistor, Electrical engineering, Converters, Switching converters, MESFETs, Boost converter, DC-DC power converters, MESFET, business, Electrical efficiency
Abstract

A detailed investigation of the switching characteristics for high frequency power devices based on different technologies has been provided: BJT, MOSFET, and MESFET/HEMT structures are considered. Advantages of GaAs power switches over silicon ones have been established and illustrated. Hybrid technology prototypes of DC-to-DC power converters operating above 10 MHz and exclusively using GaAs components have been realized: for a nonoptimized boost converter operating at 100 MHz, a power efficiency of 54% has been achieved with a 6 V/12 V conversion ratio and an output power of 1.5 W. For optimized prototypes, using high frequency assembly techniques, an efficiency of 80% at 50 MHz, 74% at 100 MHz and 60% at 250 MHz have been obtained with 6 V/12 V and 3 W.

Published
2001
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