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Profiling side-channel attacks in which an adversary creates a “profile” of a sensitive device and uses such profile to model a target device with similar implementation has received the lion’s share of attention in the recent years. In particular, template attacks are known to be the most powerful profiling side-channel attacks from an information theoretic point of view. When launching such attack, the adversary first builds a model based on the leakage of the profiling (training) device in his disposal which is then exploited in the second phase of the attack (i.e., matching) to extract the key from the target device. Discrepancies between the device used for modeling and the target device affect the attack success. The effect of process variation and temperature misalignment between the profiling and target devices in the template attack’s success has been studied extensively in literature, while the impact of device aging on the template attack’s success is yet to be investigated thoroughly. This paper moves one step forward and studies the impact of device aging, mainly Bias temperature Instability (BTI) and Hot Carrier Injection (HCI), in the devices that have been protected against power analysis attacks via dual rail logics. In particular, we focus on the Wave Dynamic Differential Logic (WDDL) circuits, and via extensive transistor-level simulations we will show how device aging misalignments between the profiling and target devices can hinder template attacks for both unprotected and WDDL protected counterparts. We mounted several attacks on the PRESENT cipher, with and without WDDL protection, at different temperatures and aging times. Our results shows that the attack is more difficult if there is an aging-duration mismatch between the training and target devices, and the attack-efficiency decrease is especially significant for mismatches of few weeks.

International audience

International audience; Analog-to-Feature (A2F) conversion is an attractive alternative for the significant reduction of energy consumed by wireless communication systems during data transfer from sensor to aggregator. This work illustrates the simulation results of anomaly detection in ECG signals via A2F conversion based on Non-Uniform Wavelet Sampling (NUWS). Moreover, another application is envisioned to show the genericity of the proposed converter and determine its parameters for a circuit design.

In modern cloud data centers, reconfigurable devices (FPGAs) are used as an alternative to Graphics Processing Units to accelerate data-intensive computations (e.g., machine learning, image and signal processing). Currently, FPGAs are configured to execute fixed workloads, repeatedly over long periods of time. This conflicts with the needs, proper to cloud computing, to flexibly allocate different workloads and to offer the use of physical devices to multiple users. This raises the need for novel, efficient FPGA scheduling algorithms that can decide execution orders close to the optimum in a short time. In this context, we propose a novel scheduling heuristic where groups of tasks that execute together are interposed by hardware reconfigurations. Our contribution is based on gathering tasks around a high-latency task that hides the latency of tasks, within the same group, that run in parallel and have shorter latencies. We evaluated our solution on a benchmark of 37500 random workloads, synthesized from realistic designs (i.e., topology, resource occupancy). For this testbench, on average, our heuristic produces optimum makespan solutions in 47.4% of the cases. It produces acceptable solutions for moderately constrained systems (i.e., the deadline falls within 10% of the optimum makespan) in 90.1% of the cases.

Embedded systems utilize Physically Unclonable Functions (PUFs) for authentication and identification purposes. However, modeling PUFs’ behavior via machine-learning methods has received utmost attention. Current research on modeling PUFs mainly targets a single PUF instance (PUF producing a single-bit response per query). It is admittedly more challenging to attack multi-bit parallel PUFs (with \(M>1\) PUF instances). In this work, we first target a multi-bit (mainly \(M=2\)-bit) parallel arbiter-PUF using its power traces, then introduce a hybrid countermeasure, combining Dual Rail Logic and Randomized Initialization Logic mechanisms, to thwart such attack. In addition, we explore Randomized Arbiter Swapping and Randomized Response Masking mitigation techniques for providing further protection for parallel PUFs against modeling attacks. To mimic the PUFs’ behavior in real silicon, we add noise artificially in our simulations. The results confirm the high success of the launched attack for the unprotected-PUF, and the resiliency of our countermeasures.

The test of security primitives is particularly strategic as any bias coming from the implementation or environment can wreck havoc on the security it is intended to provide. This paper presents how some security properties are tested on leading primitives: True Random Number Generation (TRNG), Physically Unclonable Function (PUF), cryptographic primitives and Digital Sensor (DS). The test of TRNG and PUF to ensure a high level of security is mainly about the entropy assessment, which requires specific statistical tests. The security against side-channel analysis (SCA) of cryptographic primitives, like the substitution box in symmetric cryptography, is generally ensured by masking. But the hardware implementation of masking can be damaged by glitches, which create leakages on sensitive variables. A test method is to search for nets of the cryptographic netlist, which are vulnerable to glitches. The DS is an efficient primitive to detect disturbances and rise alarms in case of fault injection attack (FIA). The dimensioning of this primitive requires a precise test to take into account the environment variations including the aging.

Embedded technologies such as IoTs, connected cars or medical equipment are often executed in constrained environment with limited resources. The high demand of security makes cryptography essential. Moreover, the security must consider physical attacks as these objects are physically accessible and can be tampered with. Lightweight Cryptography (LWC) proposes interesting candidates for securing the communications in constrained environments. As many lightweight cryptographic algorithms have been proposed with closed architectures, the features of agility and genericity could be considered. Moreover, a high robustness against side-channel analysis (SCA) is required when the connected object executes sensitive applications or manipulates private data.In this work, we propose the use of Rotating SBox Masking (RSM) protection as a generic protection that would fit most lightweight block cipher, more specifically those using 4×4 substitution boxes. This protection is developed as an extension to the RISC-V ISA through the use of additional generic instructions. This specific instruction set was implemented on the VexRisc core processor and tested with a protected implementation of the PRESENT cipher. It is easily portable to most nibble-based LWC cipher types. The security analysis of this secure RISC-V processor showed that SCA were impossible with up to 1 million traces.

In this paper, we report on a method for obtaining faults using Laser Fault Injection (LFI) in a 32-bit Microcontroller (MCU) from the Flash interface to the execution pipeline via the AHB bus. Different fault behaviors were obtained at six positions along the instruction channel. Instruction(s) were observed to be faulted with a reproducibility of 100% at each position. By collecting the faults on all the positions together and analyzing their behaviors, the faults were identified and characterized. The faults on the Flash interface buffer are different depending on the cache operation modes. When the cache is disabled, the fault is related to a block of 32 bits, whereas when the cache is enabled, the fault is related to a block of 64 bits. Two fault models, namely, replay and skip of instructions block were obtained depending on the injection position. The fault happening at the AHB bus is with a block of two instructions in both cache operation modes. Depending on the injection position, two fault models of replay and skip of two instructions were also observed. The faults on the core pipeline are related to a single instruction. The fault behavior is such that both the fetch and execution stages were faulted. The skip of a single instruction was obtained by faulting either the fetch or the execution stage of the core pipeline. By increasing the Pulse Width (PW), tens to more than one hundred of instructions were faulted at each position. The impacts of LFI parameters such as the PW and the power on the faults were studied. In addition, we compared skip fault models achieved at different positions. Our results illustrate the spatial and temporal accuracy of the LFI, thus pointing out the vulnerable positions and unveiling information of the device architecture.

In this paper, we present a method to obtain a new Laser Fault Injection (LFI)-induced fault model: replay of instructions on a 32-bit Microcontroller (MCU). This method allows a potential adversary to replay a block of two or four instructions with a fault rate up to 100%. These faults are induced by laser pulses and cause the instructions updating process of a Flash buffer to fail. As a result, the new instructions failing to be stored in the Flash buffer, the previous ones are replayed. We deeply studied the properties of this replay fault model by many experiments of laser fault injections. We have notably shown that the sensitivity window is proportional to the laser Pulse Width (PW), and that up to 20 instructions in a row were tested to be overwritten due to replaying five times the block of four instructions. The effects of the laser power and cache status (enabled or disabled) are also presented. Finally, we proposed and assessed a simple method to detect the LFI-induced replay faults using a hardware counter with different increments. Our results extend the ability of LFI on MCU, illustrating the accuracy and reproducibility of LFI.

International audience

To enhance the security of digital circuits, there is often a desire to dynamically generate, rather than statically store, random values used for identification and authentication purposes. Physically Unclonable Functions (PUFs) provide the means to realize this feature in an efficient and reliable way by utilizing commonly overlooked process variations that unintentionally occur during the manufacturing of integrated circuits (ICs) due to the imperfection of fabrication process. When given a challenge, PUFs produce a unique response. However, PUFs have been found to be vulnerable to modeling attacks where by using a set of collected challenge response pairs (CRPs) and training a machine learning model, the response can be predicted for unseen challenges. To combat this vulnerability, researchers have proposed techniques such as Challenge Obfuscation. However, as shown in this paper, this technique can be compromised via modeling the PUF's power side-channel. We first show the vulnerability of a state-of-the-art Challenge Obfuscated PUF (CO-PUF) against power analysis attacks by presenting our attack results on the targeted CO-PUF. Then we propose two countermeasures, as well as their hybrid version, that when applied to the CO-PUFs make them resilient against power side-channel based modeling attacks. We also provide some insights on the proper design metrics required to be taken when implementing these mitigations. Our simulation results show the high success of our attack in compromising the original Challenge Obfuscated PUFs (success rate > 98%) as well as the significant improvement on resilience of the obfuscated PUFs against power side-channel based modeling when equipped with our countermeasures.

International audience; One major advance in software security would be to use robust processors which could assist the code developer to thwart both cyber and physical attacks. This paper presents a hardware-based solution which increases the security by checking the integrity of executed code on any microcontroller. Unlike other Control Flow Integrity (CFI) protections, this solution does not require modifications of the CPU pipeline, but relies on monitoring the interface between the processor and its instruction cache. The integrity of the execution flow and the instruction sequences (called Basic Blocks) is checked by hardware with precomputed metadata. Another module is dedicated to speed up the access to these metadata. This paper shows the effectiveness of the solution as the impact is as much as 21% in average on the execution time at the price of using memory space to store metadata along with the code.

Physically Unclonable Functions (PUFs) are well-known to be solutions for silicon-level anti-copy applications. However, as they are sensitive components, they are the obvious target of physical attacks. Thus, they shall be well protected. In this work we discuss the use case of key generation with a Loop PUF. We discuss the Loop PUF’s efficiency and efficacy. We analyze it with respect to several known attacks like side-channel and machine learning attacks, and show that in all considered cases it either natively resists or can be protected. We also show that perturbation attempts should be within the scope of likely attacks, hence the PUF shall be protected against tampering attacks as well. Also for this attack scenario we highlight the salient features of the Loop PUF and explain how its mode of operation natively empowers it to resist such attacks.

International audience

International audience; Physical Unclonable Functions (PUFs) provide means to gen-erate chip individual keys, especially for low-cost applications such as theInternet of Things (IoT). They are intrinsically robust against reverseengineering, and more cost-effective than non-volatile memory (NVM).For several PUF primitives, countermeasures have been proposed to mit-igate side-channel weaknesses. However, most mitigation techniques re-quire substantial design effort and/or complexity overhead, which can-not be tolerated in low-cost IoT scenarios. In this paper, we first ana-lyze side-channel vulnerabilities of the Loop PUF, an area efficient PUFimplementation with a configurable delay path based on a single ringoscillator (RO). We provide side-channel analysis (SCA) results frompower and electromagnetic measurements. We confirm that oscillationfrequencies are easily observable and distinguishable, breaking the se-curity of unprotected Loop PUF implementations. Second, we presenta low-cost countermeasure based on temporal masking to thwart SCAthat requires only one bit of randomness per PUF response bit. The ran-domness is extracted from the PUF itself creating aself-secured PUF.The concept is highly effective regarding security, low complexity, andlow design constraints making it ideal for applications like IoT. Finally,we discuss trade-offs of side-channel resistance, reliability, and latency aswell as the transfer of the countermeasure to other RO-based PUFs

Fault attacks have raised serious concern with the growing amount of connected devices. Even a small vulnerability might compromise a complete network. It is therefore important to secure all the devices in the connected architecture. A solution to this problem is presented in this paper where we provide a hardware framework, called Smart Monitor, that utilizes a set of sensors (digital or physical) placed on the chip alongside the security target to be protected. The framework continuously monitors the status of the sensors and its Artificial Intelligence (AI) core produces two outputs viz. presence of a fault and type of detected perturbation. The types of attack sources can be electromagnetic, clock-glitch, laser, temperature, etc. In this work we utilize Electro-Magnetic (EM) and Clock-Glitch (CG) as sources of fault injections. Both attacks are performed in multiple settings to increase attack diversity. The framework is able to detect the presence of an attack with 92% accuracy for mixed or multiple attack sources, and further classify the type of perturbation with 78% accuracy keeping the false positive rate at 0%. Overall, this two-stage detection framework is a cost-effective countermeasure that can be deployed easily in any integrated circuit to safeguard against multiple fault attacks. The AI core is further evaluated for consistency in performance on hardware using High Level Synthesis (HLS), as a proof-of-concept, emulating real-world scenario.

Electromagnetic fault injection (EMFI) is an efficient technique to alter the behavior of microcontrollers in order to extract secret informations. Compared to fault injection techniques based on laser shots, it requires less device preparation but is a priori less accurate. Indeed, the related works on EMFI gives rather imprecise information, notably concerning the fault models and the link between the configuration and the faulted instructions. We will see in this paper that it is possible to get precise fault models by characterizing the sensitivity of a 32-bit microcontroller based on Cortex-M4 under EMFI. It is notably shown that it is relatively easy to corrupt the 128-bit instruction line buffer of four 32-bit or eight 16-bit instructions before being executed. The experimental results highlight the feasibility of well known fault models by playing with electrical and spatio-temporal parameters of the EMFI setup. In particular, we demonstrate how it is possible to target a specific instruction among those contained in the instruction buffer.

One way for an attacker to break a system is to perturb it. Expected effects are countermeasure deactivation or data corruption to disclose sensitive information. The prevention of such actions relies on detection of abnormal operating conditions. Digital sensors can play this role. A digital sensor is built out of the very same standard cells as the user logic to be protected. This ensures the advantage that the sensor and the user logic are exposed to the same stress. Balancing True positives and False negatives is a tough question in field of sensors. This is a general issue, and the best way to mitigate this paradox is to thoroughly investigate their properties, through simulations and real experiments. This results in characterizations, which in turn allows for intuitions on how to handle sensing values. In this paper, we exhibit the complex relationships between propagation times in logic and environmental conditions. Those results reinforce the relevance of the digital sensor versus the adversarial manipulation of environmental conditions: fewer false alarms are raised even if temperature (resp. voltage) is extreme, provided the effect is balanced by voltage (resp. temperature). Owing to the complex relationship between propagation delays, temperature and voltage, this cannot happen with a set of independent temperature and voltage sensors.

The silicon primitives known as Physically Unclonable Functions (PUFs) are used for various security purposes including key generation, device authentication, etc. Due to the imperfections in manufacturing process, PUFs produce their unique outputs (responses) for given input signals (challenges) fed to identical circuitry designs. Although PUFs are deployed to preserve security and are assumed to be unclonable, their functionality may still be compromised by modeling attacks. However, such attacks only target one single PUF aiming at reversing its behavior (based on a subset of its challengeresponse pairs), and are not useful for attacking other PUFs. Moreover a subset of the target PUF’s response has to be known by the attacker. This paper moves one step forward and investigates the possibility of Cross-PUF attacks in which a particular PUF’s power fingerprints can be used to break another PUF’s security. In these Cross-PUF attacks, the attacker has at his disposal a reference PUF, and uses its power side-channel to train a machine learning model which can be deployed to attack other identical PUFs. The experimental results show the high success of the proposed attacks even in presence of noise and temperature differences between the target PUF and the one used to train the model. We target arbiter-PUFs but we deduce that the findings extend to all its derivatives, e.g., XOR-PUFs and Feed-Forward-PUFs.

The integrated circuits can be exposed to various stresses during run-time due to unexpected environmental conditions or attacks. Ensuring that a circuit is not working out-of-specification via sensing its operating conditions, e.g., temperature and voltage, is highly useful in detecting anomalies. Analog sensors have been used to monitor the operating conditions for a long time, however, weaknesses including lack of portability to thin technology nodes, costly & complex calibration process, and low attack resistance make such sensors inefficient. Digital sensors, via considering the temperature and voltage effects altogether instead of treating each separately, have been demonstrated as a qualified replacement. In this paper, we develop an integrated framework for continuous monitoring of the operating voltage and temperature of each chip. The framework includes an embedded on-chip sensor circuitry along with a Neural Network model that quantifies the temperature and voltage values via processing the data collected by this sensor. The experimental results confirm the high accuracy of the proposed framework in tracking on-chip voltage and temperature variations, i.e., with the average error of 0.014V in a range of 0.65V to 1.4V, and the average error of 3.9°C in a range of -10°C to 150°C, respectively.

Laser injection is a powerful fault injection technique with a high spatial accuracy which allows an adversary to efficiently extract the secret information from an electronic device. The control and the repeatability of faults requires the attacker to understand the relation of the fault model to the setup (notably the laser spot size) and the process node of the target device. Most studies on laser fault injection report fault models resulting from a photo-electric current in CMOS transistors. This study provides a black-box analysis of the effect of a photo-electric current in floating-gate transistors of two embedded NOR Flash memories from two different manufacturers. Experimental results demonstrate that single-bit bit-set faults can be injected in code and data without corrupting the Flash memory, even with a laser spot of more than 20 µm in diameter, which is several orders of magnitude larger than the process node of the floating-gate transistors in the experiments. This article also presents the specifics of performing a "safe-error" attack on AES, leveraging the previously detailed single-bit bit-set fault model.

Detection of abnormal behaviors is essential in complex and/or strategic systems requiring a high level of safety and security. Sensing environmental conditions to ensure that the device is not operating out-of-specifications is highly useful in detecting anomalies caused by failures or malevolent actions. In this regard, digital sensors (DSs) are particularly attractive as they are portable and can be easily calibrated. In contrast to analog sensors, DSs have an interesting property that considers the operating environmental conditions as a whole, i.e., they are sensitive to temperature, voltage, and process altogether, without precise knowledge about each. This property endows DSs with fewer false positives compared to analog sensors. This article studies a low-cost DS, discusses its presilicon architecture and post-silicon calibration such that it detects system failures accurately in the designer’s preferable range of operating conditions. The impact of aging in this sensor is studied extensively. Tradeoffs between false positive and undetection rates are discussed. As an example, we target the substitution box (S-Box) of the PRESENT cipher assuming that it can be the target of fault injection attacks launched via abruptly changing the operating temperature and voltage. We show that such malfunction can be accurately detected by our DS, i.e., with a very negligible percentage of false and missed alarms (

Lightweight Cryptography (LWC) is suitable for IoTs which require a high level of security while keeping a low complexity. Many lightweight cryptographic algorithms have been proposed to satisfy these requirements. But there is currently no emerging standard concerning the symmetric block ciphering, as every algorithm has its own advantage. For instance one can be optimized for low latency, another one for low complexity but requires more rounds to be cryptographically secure to the detriment of throughput. Hence, a processor able to cope with all the algorithms should be ideal to provide agility, performance and security while keeping an affordable complexity. We present in this paper a specific execution unit of the RISC-V processor which is able to run the most common lightweight 64-bit block ciphers. The gain in performance can reach over a hundred compared to the reference architecture. The acceleration takes advantage of five specific instructions which can easily be adapted to the execution unit of a VexRiscv architecture. The complexity can double when implementing the new execution unit, but provide a high degree of agility and performance when executing most of lightweight cryptographic implementations.

International audience; One of the main challenges in the field of wireless sensors is to increase their battery life. Analog-to-feature (A2F) conversion is an acquisition method thought for IoT devices, that perform classification tasks at sub-Nyquist rate, by extracting relevant features in the analog domain and then performing the classification step in the digital domain. Current A2F solutions are designed for a specific application, this paper proposes a method to design a generic A2F converter usable for several signal types. In order to extract information for classification task, we propose to use non uniform wavelet sampling, its drawback is that it brings redundancy and irrelevant information. To reach our goal of decreasing power consumption, we need to extract a small set of relevant features for classification. To achieve this, several features selection algorithms are tested for electrocardiogram (ECG) anomalies detection. We demonstrate that the detection rate of ECG anomalies can reach 98% with less than 10 features extracted.

Recent wireless architectures have increased requirements in terms of power consumption and linearity. These requirements concern specially the power amplifier (PA) responsible for driving the antenna. One architecture proposed for this role is the outphasing amplifier, which realizes linear amplification using non-linear components. To generate the waveforms required by the switched-mode outphasing architecture, the Digital Interpolating Phase Modulator (DIPM) was proposed recently. It works by reconstructing a constant amplitude RF signal using several DSP engines. However, the authors only describe an implementation with four signal processing engines by hypothesis. In this paper, an implementation of the DIPM algorithm is developed, alongside an exploration on the number of signal processing engines used. Furthermore, the digital design is synthesized in two different process technologies to contrast power and area utilization. Our simulations confirm their choice of number of engines if power is a constraint. However, other requirements, such as technology used, may lead to different solutions.

Timely notification of abnormal behaviors is essential in strategic systems requiring a high level of safety and security. Sensing environmental conditions to ensure that the device is not operating out-of-specifications is highly useful in detecting anomalies caused by failures or malevolent actions. Digital sensors consider the operating environmental conditions as a whole, i.e. they are sensitive to temperature, voltage and process altogether, without precise knowledge about each. This paper proposes a low-cost digital sensor that can detect system failures accurately in the designer's preferable range of operating conditions. Our experimental results show the high accuracy of this sensor in detecting circuits failure which occurred due to change of the operating temperature and supply voltage.

Leadless Cardiac Pacemakers (LCP) have the potential to revolutionize Cardiac Rhythm Management (CRM). Current LCPs can only pace a single location of the heart limiting their use to patients requiring single-chamber stimulation. A Multi-node system of synchronized LCPs could be used in a significantly larger patient population. Synchronization using standard communication techniques involves high power consumption decreasing the longevity of the device. In this work, we investigate Galvanic Intra Body Communication (IBC) as a method to synchronize multi-node LCP systems. First, an accurate computational torso model was used for quasi-static simulations to estimate channel pathloss in the frequency range [40 kHz-20 MHz]. The model was then verified with in-vivo measurements using a novel experimental setup, where two LCP devices were placed in the right atrium, right ventricle and left ventricle. All channels involved in a potential multi-node LCP system were characterized. The orientation of the transducers relative to each other had a great impact on the results, with the attenuation level ranging between 55 dB and 70 dB between the best and worst orientations. The best results were achieved in the MHz range. Coupled with the fact that it does not require additional electrodes, this study suggests Galvanic IBC be superior to conventional communication methods for LCP devices. This analysis defines a methodology for galvanic IBC channel characterization for LCP systems, which is an important step for the design of efficient transceivers for IBC applications. More experiments with larger datasets are needed to bring this method to practice.

Thanks to the imperfections in manufacturing process, Physically Unclonable Functions (PUFs) produce their unique outputs for given input signals (challenges) fed to identical circuitry designs. PUFs are often used as hardware primitives to provide security, e.g., for key generation or authentication purposes. However, they can be vulnerable to modeling attacks that predict the output for an unknown challenge, based on a set of known challenge/response pairs (CRPs). In addition, an attacker may benefit from power side-channels to break a PUFs' security. Although such attacks have been extensively discussed in literature, the effect of device aging on the efficacy of these attacks is still an open question. Accordingly, in this paper, we focus on the impact of aging on Arbiter-PUFs and one of its modeling-resistant counterparts, the Voltage Transfer Characteristic (VTC) PUF. We present the results of our SPICE simulations used to perform modeling attack via Machine Learning (ML) schemes on the devices aged from 0 to 20 weeks. We show that aging has a significant impact on modeling attacks. Indeed, when the training dataset for ML attack is extracted at a different age than the evaluation dataset, the attack is greatly hindered despite being performed on the same device. We show that the ML attack via power traces is particularly efficient to recover the responses of the anti-modeling VTC PUF, yet aging still contributes to enhance its security.

In this paper, we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies, which minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results of two test circuits, a chain of inverters and a ripple carry adder, show that by using this sizing approach, the energy per operation can be reduced in more than 50% in a wide range of target performances. We use a 28-nm ultra-thin body and box fully depleted silicon-on-insulator technology and we show that the combination of supply voltage scaling, backplane biasing, and length biasing can be combined to obtain extremely robust (variability is almost halved) and energy efficient digital circuits. We also show simulation results for predictive technology models to show that the technique is also compatible with conventional bulk technologies.

Sensing environmental variables is an important step for autonomous devices which operate in different conditions. For this purpose, the digital chips embed sensors, preferably digital for portability reasons, to ensure that they are not operating out-of-specifications. However, a digital sensor is exposed to various stress as well as aging during its lifetime. Aging makes the sensors’ output deviate from the original intended one, resulting in an incorrect report of the operating condition and in turn improper actions based on such reports. This paper presents a thorough study on the effect of aging on digital sensors. We first propose two low-overhead characterization schemes for these sensors. Then, we investigate the accuracy of such characterizations on different processes, voltages, temperatures and aging conditions. Our results show that sensors’ ability to detect attacks (as well as false detections) varies with aging, notably in the first 5 years of usage. Indeed, comparing new versus aged sensor shows that 3% to 12% of the alarms that would raise if the sensor were new, will not be fired for a 5 year old device, while 15%-25% false alarms are raised for the device after 5 years of usage. This brings a great concern to the reliability as well as the security of the digital sensors which can not be used as is after aging. It is also shown that these results stay the same whatever the variation of the process. Consequently, it is recommended to associate an aging correction to digital sensors, such as in-field calibration techniques, and/or sensor replication.

International audience; Physically Unclonable Functions (PUFs) allow to extract unique fingerprints from silicon chips. The applications are numerous: chip identification, chip master key extraction, authentication protocol, unique seeding, etc. However, secure usage of PUF requires some precautions. This paper reviews industrial concerns associated with PUF operation, including those occurring before and after market. Namely, starting from PUF “secure”specifications, aligned with state-of-the-art standards, we explore innovative techniques to handle enrollment and subsequent PUF queries, in nominal as well as in adversarial environment.

The complexity of heterogeneous Multi-Processor Systems-on-Chip stretches the limits of software development solutions based on sequential languages such as C/C++. While these are still the most widely used languages in practice, model-based solutions appear to be an efficient alternative. However, the optimized compilation of models for multi-processor systems still presents many open research problems. Among others, static data-flow analyses for models require the adaptation of traditional algorithms used in program analysis (iterative and worklist algorithms). These algorithms operate on Control-Flow Graphs with a unique start node (i.e., a node without predecessors) and assume that every basic block is reachable from this start node.

This study investigates a new side-channel leakage observed in the inner rounds of an unrolled hardware implementation of block ciphers in a chosen-input attack scenario. The side-channel leakage occurs in the first round and it can be observed in the later inner rounds because it arises from path activation bias caused by the difference between two consecutive inputs. Therefore, a new attack that exploits the leakage is possible even for unrolled implementations equipped with countermeasures (masking and/or deglitchers that separate the circuit in terms of glitch propagation) in the round involving the leakage. We validate the existence of such a unique side-channel leakage through a set of experiments with a fully unrolled PRINCE cipher hardware, implemented on a field-programmable gate array (FPGA). In addition, we verify the validity and evaluate the hardware cost of a countermeasure for the unrolled implementation, namely the Threshold Implementation (TI) countermeasure. Published version

International audience; This paper presents a ranging test conducted in a standard indoor environment using an ultra-wideband (UWB) radar system. The position is determined by jointly estimating the distance using the Energy Detection (ED) method, and the Azimuth angle using Phase Correlation (PC) method. The obtained results show that this UWB ranging system can improve the angular resolution compared to traditional Indoor Localization Systems (ILSs).

Cryptography is a key element to the development of secure communication in embedded environments such as connected cars and IoT. For some specific applications specific Lightweight Block Ciphers (LBC) have emerged. Those algorithms have been designed to be less resource consuming and more flexible than standard cryptographic algorithms. In order to keep a high levels of performance for software implementation of those LBC, we propose to enhance the instruction set of microprocessors by adding custom instructions. This would allow the system designer to find the best compromise between flexibility requirements and efficiency in terms of throughput and latency. This paper first presents a classification of LBC according to their specific operations. Then, based on the open RISC-VISA, we propose a set of custom instructions to enhance LBC execution. The comparison of both execution time and throughput between different levels of processor customization is presented. Our results showed a significant gain as the execution time can be reduced by a factor between 20 and 100 for some classes of LBC.

Side-channel analysis and fault injection attacks are two typical threats to cryptographic implementations, especially in modern embedded devices. Thus there is an insistent demand for dual side-channel and fault injection protections. As it is known, masking scheme is a kind of provable countermeasures against side-channel attacks. Recently, inner product masking (IPM) was proposed as a promising higher-order masking scheme against side-channel analysis, but not for fault injection attacks. In this paper, we devise a new masking scheme named IPM-FD. It is built on IPM, which enables fault detection. This novel masking scheme has three properties: the security orders in the word-level probing model, bit-level probing model, and the number of detected faults. IPM-FD is proven secure both in the word-level and in the bit-level probing models, and allows for end-to-end fault detection against fault injection attacks.Furthermore, we illustrate its security order by linking it to one defining parameters of linear code, and show its implementation cost by applying IPM-FD to AES-128.

International audience; Electromagnetic fault injection is a growing topic when it is applied to jeopardize the security of integrated circuit. Indeed, if the main part of the process will focus on the hardware efficiency of the near-field probes, tweaking properties of the electromagnetic disturbance can also lead to the success of the attack. In this paper, we are presenting characterization results of intentional electromagnetic interference by measuring its impact within the target, and more precisely on the propagation delay of a combinational logic path. The evaluation of the impact shows that the electromagnetic coupling between the probe and the integrated circuit strongly depends on the characterized properties.

Hardware Trojan Horses and active fault attacks are a threat to the safety and security of electronic systems. By such manipulations, an attacker can extract sensitive information or disturb the functionality of a device. Therefore, several protections against malicious inclusions have been devised in recent years. A prominent technique to detect abnormal behavior in the field is run-time verification. It relies on dedicated monitoring circuits and on verification rules generated from a set of temporal properties. An important question when dealing with such protections is the effectiveness of the protection against unknown attacks. In this paper, we present a methodology based on automatic generation of monitoring and formal verification techniques that can be used to validate and analyze the quality of a set of temporal properties when used as protection against generic attackers of variable strengths.

International audience; In recent wireless communication standards (4G, 5G), the growing need for dynamic adjustments of transmission parameters (e.g., modulation, bandwidth, channel coding rate) makes traditional static scheduling approaches less and less efficient. The reason being that precomputed fixed mapping and scheduling prevent the system from dynamically adapting to changes of the operating conditions (e.g. wireless channel quality, available bandwidth). In this paper, we present Odyn, a hybrid approach for the scheduling and memory management of periodic dataflow applications on parallel, heterogeneous, Non-Uniform Memory Architecture (NUMA) platforms. In Odyn, the ordering of tasks and memory allocation are distributed and computed simultaneously at run-time for each Processing Element. Odyn also proposes a mechanism to prevent deadlocks caused by attempts to allocate buffers in size-limited memories. This technique, based on the static computation of exclusion relations among buffers in a target application, removes the need for backtracking that is typical of dynamic scheduling algorithms. We demonstrate the effectiveness of Odyn on a testbench that simulates the interactions of randomly generated concurrent applications. We also demonstrate its deadlock prevention technique on a selection of use cases.

International audience; Fault injection techniques allow an attacker to alter the behavior of an electronic device in order to extract confidential information or be granted unauthorized privileges. To this end, local electromagnetic fault injections (EMFI) are commonly used to corrupt or prevent the execution of instructions.However, little attention is devoted to practical data corruption. This article investigates the local effects of EMFI on data transfer from the Flash memory to the 128-bit data buffer of a cortex-M microcontroller. We demonstrate that the corrupted bits are closely related to the location of the injection probe, allowing us to set or reset from 0 to 128 bits with a byte- level precision. Moreover, the spatial and temporal accuracy of the injection technique allowed us to target the data prefetch mechanism without corrupting the code execution.We highlight the efficiency of the derived fault model with three practical case studies. Firstly, we demonstrate precise key- zeroing and key-setting capability, with further extension to a DFA on the secret key of a cipher from Biham and Shamir, that was never implemented practically. Next, we report practical persistent faults on ARM microcontroller, which allows an attacker to retrieve the secret key of a cipher with a single successful injection.

International audience; Cryptography is a key element to the development of secure communication in embedded environment such as within or between connected cars. In such constrained devices standard cryptographic algorithms have been considered too costly which lead to the emergence of specific Lightweight Block Ciphers (LBC). The lack of standards alongside industry's desire to use uniquely tweaked LBC calls for a generic and efficient implementation of those algorithms. Microprocessors are a part of most of these embedded systems which allows them to implement any of these algorithms but not efficiently way as it lacks specific instructions. For instance, the RiscV is an open source ISA which can be used in these microprocessors and is currently being enhanced by research through extensions. In this work we propose the study of this ISA and the development of an extension for efficient implementation of LBC. From the state of the art [5], [7] we have selected some LBC based on the following criteria: at least a 128-bit key for security and a 64-bit block size to limit the necessary resources. In order to identify useful extensions, we first identified which parts of LBC are slow when implemented in pure software, and how common they are in state of the art LBC. We only studied the datapath of the cipher as we considered the key scheduling to be part of preprocessing. We used a software implementation of each of the studied algorithms to isolate the costly parts of the ciphers. The computation time was evaluated in number of RiscV assembly language instructions. Studied LBC algorithms exhibit 3 main computation steps: • The key addition which is a simple XOR and doesn't require additional instructions • 8 or 16 4x4 Sbox (common for LBC) which can be implemented as LUT and can be accelerated thanks to the addition of a specific (SIMD) LUT instruction • The diffusion is generally not trivial to implement in pure software and as it can be quite different from one algorithm to the other it is not obvious to provide a unique extension to implement it.

The Physically Unclonable Function (PUF) has become an inescapable security primitive, as it generates a fingerprint unique to each device, and is natively robust against reverse engineering attacks. However it suffers from many flaws due to a native lack of reliability and sensitivity against modeling and physical attacks. In the state-of-the-art, the enhancement of reliability involves the use of a helper data which takes advantage of Error-Correcting Codes (ECC), situated after the entropy source, thus increasing the overall PUF complexity and creating leakages exploited by Side Channel Attacks.This paper presents a new method to generate Helper Data, situated before the entropy source, which does not use ECC but still improves drastically the reliability of the PUF. It also provides high entropy and proven resistance against the attacks on the helper data. This method applies to "strong" delay PUFs used as master key generators, thus unsensitive to modeling attacks (the PUF responses are never disclosed). The validation has been done on real ASIC devices fabricated in CMOS 45 nm technology and shows that the reliability can be as low as 10−8 of Bit Error Rate.

International audience

A novel analytical approach is used to determine a new boundary condition for optimal operation of a class B Chireix outphasing PA. In the proposed method, a threshold outphasing angle is defined as a new design parameter and used to optimize the power stage in an outphasing system.

International audience

In this work, a novel approach to reduce the complexity of memory polynomial model is presented. The proposed technique, named the coefficient decomposition (CD) technique, is based on reducing the search space for the memory polynomial coefficients based on memory effects generation mechanism. In this paper, the technique is demonstrated for power amplifier of classes A and AB. In this case, the physical analysis shows that the conventional two-dimensional coefficient architecture of the memory polynomial could be simplified into a one dimensional architecture while keeping almost the same accuracy. The performance of the proposed approach is demonstrated and compared with other models using a 30 dBm commercial power amplifier with 20 MHz and 60 MHz LTE signals. The measurements and simulations showed that, the presented model achieves −34.2 dB of NMSE while needing only 13 coefficients compared with 25 needed for a memory polynomial model. Also, the DPD performance of the proposed model is the same as memory polynomial model and comparable with high complexity models like the PLUME and GMP.

International audience; With the CMOS technology reaching its limits, the design of cyber physical systems is becoming more and more complex. Securing the performance in terms of resolution, speed or flexibility would require a more intensive use of digital assistance to compensate for the increased challenges on the RF and analog parts.This tutorial will provide an overall overview of how to design, size and implement a digital assistance to compensate for a given non-ideality. All the main steps will be covered from the modeling approach to the implementation in fixed point. The major caveats for each topic will be discussed in order to materialize the limits of the presented methods and models. Concrete examples as well as live experimental demos will be presented for several applications such as Digital Pre-Distortion for Power Amplifiers, Digital correction of Stacked and Time Interleaved ADCs and Dynamic Element Matching Techniques for Digital to Analog Converters.

International audience

International audience