1. Modeling and Design of High Bandwidth Feedback Loop for dv/dt Control in CMOS AGD for GaN
- Author
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Bernardo Cougo, Nicolas Rouger, Marc Cousineaul, Frédéric Richardeau, Plinio Bau, IRT Saint Exupéry - Institut de Recherche Technologique, LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, Convertisseurs Statiques (LAPLACE-CS), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), and Centre National de la Recherche Scientifique (CNRS)
- Subjects
010302 applied physics ,Computer science ,020208 electrical & electronic engineering ,Bandwidth (signal processing) ,[SPI.NRJ]Engineering Sciences [physics]/Electric power ,02 engineering and technology ,Feedback loop ,01 natural sciences ,7. Clean energy ,Switching time ,CMOS ,EMI ,Control system ,Power electronics ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Gate driver ,Electronic engineering ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics - Abstract
International audience; The objective of this work is to show the intrinsic limitations of a CMOS technology for the realization of an Active Gate Driver (AGD) with active dv/dt control loop. Due to a theoretical study using first order models of CMOS submicron transistors, the main equations providing the link between feedback loop bandwidth and specific technology parameters are obtained. This optimization study allows us to determine the theoretical limits in terms of bandwidth and silicon area. Then, it becomes possible to determine the most appropriate switching control method to implement depending on the application requirements (high efficiency, low EMI), i.e. active feedback with adjustable gain, while ensuring suitable time delays. A feedback loop bandwidth of 1.59 GHz using an 1pF integrated capacitor to address a switching speed of 175 V/ns is demonstrated. Experimental results and simulations using accurate technology models confirms the theory. Keywords-Active gate driver, GaN, switching analysis, dv/dt, EMI, power electronics, ASIC for power IC.
- Published
- 2020