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Your search keyword '"Plinio Bau"' showing total 2 results
Start Over Author "Plinio Bau" Topic [spi.nano]engineering sciences [physics]/micro and nanotechnologies/microelectronics
2 results on '"Plinio Bau"'

1. Modeling and Design of High Bandwidth Feedback Loop for dv/dt Control in CMOS AGD for GaN

Author

Bernardo Cougo, Nicolas Rouger, Marc Cousineaul, Frédéric Richardeau, Plinio Bau, IRT Saint Exupéry - Institut de Recherche Technologique, LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées, Convertisseurs Statiques (LAPLACE-CS), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), and Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Computer science, 020208 electrical & electronic engineering, Bandwidth (signal processing), [SPI.NRJ]Engineering Sciences [physics]/Electric power, 02 engineering and technology, Feedback loop, 01 natural sciences, 7. Clean energy, Switching time, CMOS, EMI, Control system, Power electronics, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Gate driver, Electronic engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; The objective of this work is to show the intrinsic limitations of a CMOS technology for the realization of an Active Gate Driver (AGD) with active dv/dt control loop. Due to a theoretical study using first order models of CMOS submicron transistors, the main equations providing the link between feedback loop bandwidth and specific technology parameters are obtained. This optimization study allows us to determine the theoretical limits in terms of bandwidth and silicon area. Then, it becomes possible to determine the most appropriate switching control method to implement depending on the application requirements (high efficiency, low EMI), i.e. active feedback with adjustable gain, while ensuring suitable time delays. A feedback loop bandwidth of 1.59 GHz using an 1pF integrated capacitor to address a switching speed of 175 V/ns is demonstrated. Experimental results and simulations using accurate technology models confirms the theory. Keywords-Active gate driver, GaN, switching analysis, dv/dt, EMI, power electronics, ASIC for power IC.

Published
2020

2. A CMOS gate driver with ultra-fast dV/dt embedded control dedicated to optimum EMI and turn-on losses management for GaN power transistors

Author

Plinio Bau, Frédéric Richardeau, Bernardo Cougo, Davy Colin, Marc Cousineau, Nicolas Rouger, IRT Saint Exupéry - Institut de Recherche Technologique, Convertisseurs Statiques (CS), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, Centre National de la Recherche Scientifique (CNRS), Université de Toulouse (Université de Toulouse), IRT Saint Exupéry - Institut de Recherche Technologique (FRANCE), Université de Toulouse - INP, Laboratoire de Génie Electrique de Grenoble (G2ELab), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut Polytechnique de Grenoble - Grenoble Institute of Technology-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Convertisseurs Statiques (LAPLACE-CS), Institut National Polytechnique (Toulouse) (Toulouse INP), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])

Subjects
02 engineering and technology, High-electron-mobility transistor, 7. Clean energy, law.invention, Computer Science::Hardware Architecture, Computer Science::Emerging Technologies, law, EMI, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Gate driver, 0501 psychology and cognitive sciences, Power semiconductor device, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 050107 human factors, ComputingMilieux_MISCELLANEOUS, Physics, business.industry, 05 social sciences, Transistor, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Order (ring theory), 020207 software engineering, CMOS, Optoelectronics, business, Energy (signal processing)
Abstract

In this paper, a CMOS gate driver in $180\mathrm {n}\mathrm {m}$ technology is presented. The gate driver implements an integrated and independent ultra-fast $\mathrm {d}\mathrm {V}/\mathrm {d}\mathrm {t}$ control circuit dedicated to manage switch-on transients for $\mathrm {G}\mathrm {a}\mathrm {N}$ HEMT technology. In order to mitigate a detrimental effect in EMI spectrum for wide bandgap transistors, a novel method to reduce $\mathrm {d}\mathrm {V}/\mathrm {d}\mathrm {t}$ without increasing so much switching losses is proposed. A comprehensive benchmark with the classical method is also presented, where the gate driver resistance is typically adjusted. Simulations are conducted to show the feasibility of the proposed method and the amount of switching energy that can be saved. Time responses of a feedback loop lower than $200\mathrm {p}\mathrm {s}$ are expected. The preliminary characterization of the integrated CMOS circuit is shown.

Published
2018

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