1. Surface effects on split C-V measurements on SOI wafers
- Author
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Pirro, L., Ionica I., gerard ghibaudo, Sorin Cristoloveanu, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), and Rasolofoniaina, Brigitte
- Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics - Abstract
session SOI MOSFET CharacterizationO13; International audience; The experimental conditions for split C-V technique in pseudo-MOSFET configuration are investigated. Previous studies showed that the capacitance variation with frequency is dominated by the equivalent RC circuit describing the channel formation. Therefore, an extrapolation of interface trap density was not possible. Here, we demonstrate that the conductance term, measured at low frequency as a function of gate bias, is clearly influenced by the quality of the top wafer surface, potentially leading to the evaluation of interface traps.
- Published
- 2014