Search

International audience; Nowadays, multi-sensor architectures are popular to provide a better understanding of environment perception for intelligent vehicles. Using multiple sensors to deal with perception tasks in a rich environment is a natural solution. Most of the research works have focused on PC-based implementations for perception tasks and very few concerns have been addressed for customized embedded designs. In this paper, we propose a Multi-Sensor Data Fusion (MSDF) embedded design for vehicle perception tasks using stereo camera and Light Detection and Ranging (LIDAR) sensors. A modular and scalable architecture based on Zynq-7000 SoC was designed.

International audience; This paper deals with the initial phase of any multi-sensor acquisition, the sensor alignment process. We focus on extrinsic calibration of vision-based and line scan LIDAR sensors for automotive application. We investigate two research approaches for the calibration process: analytical and numeric solutions. Additionally, we present a complete implementable tool-chain, to extract the co-features for both types of sensors: line detections for cameras and segmentation process for LIDAR sensors. Moreover, we investigate the impact of the calibration accuracy on sensor fusion performance. Results of experiments using real-world data are presented.

International audience; Due to the growing complexity of Systems-on-Chip (SoC) and the increasing cost of their redesign and fabrication, industrials are urgently looking for design methodologies allowing them to identify issues early in the design flow and to explore the largest possible space of solutions. Several aspects should be taken into account in this context, among which power consumption is considered as a major concern. In this paper, we present a Model Driven Engineering (MDE) approach for early power-aware Design Space Exploration (DSE). This approach facilitates designers work by abstracting the energetic behavior of embedded systems through high-level models targeting an automatic generation of power-aware simulation code. It offers also the possibility to model dynamic power management aspects in order to use the corresponding generated code for DSE. This approach was implemented in the DSE toolkit TTool by integrating power concepts in its DIPLODOCUS UML profile and its simulator. This paper illustrates the proposed approach through a Software-Defined Radio (SDR) case study integrating the Dynamic Slack Reclamation (DSR) policy for dynamic power management. The processor power estimates obtained by the generated simulation code were compared to those obtained from physical implementation on the Xilinx Zynq-7000 platform. This comparison showed that our MDE approach allows to take efficient design decisions early in the design flow.

La présente invention concerne un procédé et un système de planification (2) d'un chemin aérien pour un aéronef (1), ledit système (2) comportant une unité d'extraction pour extraire d'une unité de stockage des premières données, lesdites premières données étant issues d'au moins une base de données « terrain » contenant des données topographiques d'une zone de vol lors d'une mission dudit aéronef (1).

International audience; The aim of this paper is to build a trajectory tracking system considering the attitude of the quadrotor. Nowadays, quadcopter is often used for taking landscape pictures. The roll pitch Euler angle of the quadcopter greatly affects the resulting pictures so that it needs to be controlled. As a limitation, the roll pitch Euler angle based on inertial reference frame is not allowed to be more than fifteen degrees. Two main factors that affect the Euler angle of quadcopter are velocity and acceleration. Therefore, the velocity and acceleration of the UAV is maintained. A linear regression method is used to determine the velocity and acceleration reference that affect the resulting Euler angle. PID (Proportional, Integral, Derivative) controller is used as the controller method for the tracking control system. Finally, the trajectory tracking and attitude control is evaluated through simulation with ROS and Gazebo.

Real-time computing systems are increasingly used in aerospace and avionic industries. In the face of power challenge, performance requirements and demands for higher flexibility, hardware designers are directed toward reconfigurable computing using field programmable gate arrays (FPGAs) that offer high computation rates per watt and adaptability to the application constraints. However, considering reconfigurable computing in the avionic design process leads to several challenges for system developers. Indeed, such technology should be validated along the verification & validation cycle starting with simulation tools, passing through the test benches and finishing with the integration phase. For each step, the FPGA can play an essential role to achieve better performances, more adaptive systems, and cost-effective solutions. In this paper, we present a seamless FPGA-centric design process for avionic equipments. Along this process, we redefine the role of the FPGA circuits to cover the simulation, the test, and the integration steps. First, reconfigurable logics are used in the frame of heterogeneous CPU/FPGA computing in order to obtain high speed-up for real-time avionic simulation. The proposed environment supports dynamic execution model enabling reconfiguration during runtime to avoid the timing constraint violation. Second, the FPGA is used as a key solution to offer versatile test benches and to converge toward unified test and simulation tools. We have designed several commercial input output intellectual property systems with dynamic runtime reconfiguration capabilities, in order to mitigate component obsolescence and to provide increased flexibility and decreased design time. Third, at the integration phase, we use the conventional tools to make profit from reconfigurable technology in embedded avionic applications in order to deliver high computation rates and to adapt their functioning mode to provide reliability, fault tolerance, deterministic timing guarantees, and energy efficiency.

International audience; The development of multiprocessor Systems on chips (MPSOC) led to increasing difficulties in system design. The optimization of energy consumption has become a primary concern. The solution is to use various techniques for optimizing energy and power. The purpose of this paper is to integrate a Dynamic Slack Reclamation technique in the application software radio which is an algorithm based on the strategy of slowing down the frequency/voltage couple on the processor. The advantage of this algorithm is that it ensures the detection of task completion and determines the quantity of delay time by comparing the worst execution time with the real time. Experimental results show that the use of a DSR algorithm increases the performance by respecting real-time constraints in terms of power consumption and energy on a real platform, OMAP 3530. In addition, the power and energy consumption is reduced up to 27% and 8% respectively for scenario 1 and scenario 2. The result also show that scenario 1 consumes 80% more energy than scenario 2.

International audience

International audience; Sophisticated embedded systems are increasingly used in defence, aerospace and avionic industries. They are responsible for control, collision avoidance, pilot assistance, target tracking, navigation and communications, amongst other functions. In this industrial field, High Performance Embedded Computing (HPEC) applications are becoming highly sophisticated and resource consuming for three reasons. First, they should capture and process real-time data from several I/O sources in parallel. Second, they should adapt their functionalities according to the application or environment variations within given Size Weight and Power (SWaP) constraints. Third, since they process several parallel I/O sources, applications are often distributed on multiple computing nodes making them highly parallel. The problem with current HPEC systems is that, they are usually built to meet the needs of a specific application, i.e., lacks flexibility to upgrade the system or reuse existing hardware resources. Due to the hardware parallelism and I/O bandwidth offered by Field Programmable Gate Arrays (FPGAs), application can be duplicated several times to process parallel I/Os, making Single Program Multiple Data (SPMD) the favorite execution model for designers implementing parallel architectures on FPGAs. Furthermore Dynamic Partial Reconfiguration (DPR) feature allows efficient reuse of limited hardware resources, making FPGA a highly attractive solution for such applications. This paper will address HPEC application design challenges and will discuss some solutions relying on FPGA technologies and referring to several industrial collaborations.

International audience; In this paper we deal with sensor alignment problems that appear when implementing sensor fusion-based autonomous vehicle perception. We focus on extrinsic calibration of vision-based and line scan LIDAR sensors. Based on state-of-art solutions, a consistent calibration toolchain is developed, with improvements (accuracy and calibration duration). Additionally, sensor alignment/calibration impact on fusion-based perception is investigated. Experimental results are provided for illustration, using real-world data.

International audience; Sorting algorithms are one of the most commonly used in computer science. They can be seen as a pillar for some applications such as decision support systems, path planning, etc. However, sorting large number of elements needs high computation rate. Consequently, accelerating sorting algorithms using hardware implementation is an interesting solution to speed up computations. The purpose of this paper is to develop a hardware accelerated version of TimSort and MergeSort algorithms from high level descriptions. The algorithms are implemented using Zynq-7000 xilinx platform as part of real time decision support for avionic applications. As experimental results, we compare the performance of two algorithms in terms of execution time and resource utilization. We showed that TimSort ranges from 1.07x to 1.16x faster than MergeSort when optimized hardware is used.

International audience; The continuous improvements in several application domains such as telecommunications, aerospace or multimedia lead to additional design constraints on power budget and architecture scalability. The heterogeneous CPU/FPGA (Central Processing Unit/Field-Programmable Gate Array) architecture is one of the most promising solutions in this context leading to high performance reconfigurable computing. In such systems, multi-core processors (CPU) provide high computation rates while the reconfigurable logic (FPGA) offers high performance and adaptability to the application real-time constraints. However, there is a lack of CAD (Computer Aided Design) tools able to deal with the development of applications on such heterogeneous systems. This research investigates the problem of the optimisation of static and run-time task mapping on a real-time computing system CPU/FPGA used to implement intimately coupled hardware and software models.

Finding the optimal 3D path of an aerial vehicle under flight mechanics constraints is a major challenge, especially when the algorithm has to produce real time results in flight. Kinematics models and Pythagorian Hodograph curves have been widely used in mobile robotics to solve this problematic. The level of difficulty is mainly driven by the number of constraints to be saturated at the same time while minimizing the total length of the path. In this paper, we suggest a pragmatic algorithm capable of saturating at the same time most of dimensioning helicopter 3D trajectories' constraints like: curvature, curvature derivative, torsion, torsion derivative, climb angle, climb angle derivative, positions. The trajectories generation algorithm is able to generate versatile complex 3D motion primitives feasible by a helicopter with parameterization of the curvature and the climb angle. An upper "motion primitives' concatenation" algorithm is presented based. In this article we introduce a new way of designing three-dimensional trajectories based on what we call the "Dubins gliding symmetry conjecture". This extremely performing algorithm will be soon integrated to a real-time decisional system dealing with inflight safety issues., {"references":["T. F. Banchoff and S. T. Lovett, Differential geometry of curves and\nsurfaces. CRC Press, 2010.","Y. Bestaoui, \"General representation of 3d curves for an unmanned aerial\nvehicle using the frenet-serret frame,\" AIAA, 2007.","P. Bezier, \"Essais de definition numeriques des courbes et surfaces non\nmathematiques,\" Systeme Unisurf, Automatisme,13, 1968.","C. L. Bottasso, D. Leonello, and B. Savini, \"Path planning for\nautonomous vehicles by trajectory smoothing using motion primitives,\"\nControl Systems Technology, IEEE Transactions on, vol. 16, no. 6, pp.\n1152–1168, 2008.","L. E. Dubins, \"On curves of minimal length with a constraint on\naverage curvature, and with prescribed initial and terminal positions and\ntangents,\" American Journal of mathematics, pp. 497–516, 1957.","M. Hwangbo, J. Kuffner, and T. Kanade, \"Efficient two-phase 3d motion\nplanning for small fixed-wing uavs,\" in Robotics and Automation, 2007\nIEEE International Conference on. IEEE, 2007, pp. 1035–1041.","V. P. Kostov, E. V. Degtiariova-Kostova et al., \"The planar motion with\nbounded derivative of the curvature and its suboptimal paths,\" Acta\nMath. Univ. Comenianae, vol. 64, no. 2, pp. 185–226, 1995.","N. Ozalp and O. K. Sahingoz, \"Optimal uav path planning in a 3d threat\nenvironment by using parallel evolutionary algorithms,\" in Unmanned\nAircraft Systems (ICUAS), 2013 International Conference on. IEEE,\n2013, pp. 308–317.","M. Shah and N. Aouf, \"3d cooperative pythagorean hodograph path\nplanning and obstacle avoidance for multiple uavs,\" in Cybernetic\nIntelligent Systems (CIS), 2010 IEEE 9th International Conference on.\nIEEE, 2010, pp. 1–6.\n[10] M. Shanmugavel, A. Tsourdos, R. Zbikowski, B. A. White, C. Rabbath,\nand N. Lechevin, \"A solution to simultaneous arrival of multiple uavs\nusing pythagorean hodograph curves,\" in American Control Conference,\n2006. IEEE, 2006, pp. 6–pp.\n[11] T. R. Wan, W. Tang, and H. Chen, \"A real-time 3d motion planning and\nsimulation scheme for nonholonomic systems,\" Simulation Modelling\nPractice and Theory, vol. 19, no. 1, pp. 423–439, 2011.\n[12] K. Yang, S. K. Gan, and S. Sukkarieh, \"An efficient path planning and\ncontrol algorithm for ruavs in unknown and cluttered environments,\"\nJournal of Intelligent and Robotic Systems, vol. 57, no. 1-4, pp. 101–122,\n2010."]}

International audience; Power consumption has become one of the major concerns in embedded systems design, especially for mobile devices, which integrate many applications leading to a high power consumption. In this context, designers have the challenge to identify power issues early in the design flow and to explore the largest possible space of power-efficient solutions. In this paper, we present a Model Driven Engineering (MDE) approach for early power-aware Design Space Exploration (DSE). This approach is based on a high-level modeling of power estimation and dynamic management aspects targeting an automatic generation of the corresponding simulation code. It was implemented in the DSE toolkit TTool by integrating power concepts in its DIPLODOCUS UML profile. The existing C++ simulation code generator was extended in order to integrate power estimation. The main objective of this article is to illustrate the potential of our approach through an MPEG-2 case study. The proposed high-level power modeling concepts were used to target two different platforms for the implementation of an MPEG-2 decoding application. The processor power estimates obtained from simulations were compared to real board measurements. This comparison showed that our MDE approach is capable of obtaining results that can be used to make early power-efficient design decisions.

International audience; In this paper we consider scheduling tasks on a multiprocessor system, taking into account communication delays. We propose a new Mixed Integer Program (MIP) formulation that drastically reduces both the number of variables and the number of constraints, when compared to the best mathematical programming formulations from the literature. In addition, we propose pre-processing procedures that generates cuts and bounds on all variables, reducing the solution space of the problem as well. Cuts are obtained by using forward and backward critical path method from project management field, while the upper bound is derived from the new greedy heuristic. Computational experience shows advantages of our approach.

International audience; In the recent decades an impressive progress was done in automation and robotic fields. Projects such as Google driverless car with “sense and avoid” capabilities or intelligent Unmanned Air Vehicle (UAV) are examples of interesting research works targeting a high degree of autonomy. In this context we underline the unavoidable requirement for improving path planning algo-rithms. Indeed, path planning is one of the essential tasks in the automation process of a system that moves in the environment while avoiding obstacles and respecting various constraints. In this paper we present a state-of-the-art of path planning in the field of automation, robotics and video games. Furthermore, we focus on widespread algorithms that can satisfy real-time constraints and dynamic re-planning.

International audience; As technology scales for increased circuit density and performance, the management of power consumption in system-on-chip (SoC) is becoming critical. Today, having the appropriate electronic system level (ESL) tools for power estimation in the design flow is mandatory. The main challenge for the design of such dedicated tools is to achieve a better tradeoff between accuracy and speed. This paper presents a consumption estimation approach allowing taking the consumption criterion into account early in the design flow during the system cosimulation. The originality of this approach is that it allows the power estimation for both white-box intellectual properties (IPs) using annotated power models and black-box IPs using standalone power estimators. In order to obtain accurate power estimates, our simulations were performed at the cycle-accurate bit-accurate (CABA) level, using SystemC. To make our approach fast and not tedious for users, the simulated architectures, including standalone power estimators, were generated automatically using a model driven engineering (MDE) approach. Both annotated power models and standalone power estimators can be used together to estimate the consumption of the same architecture, which makes them complementary. The simulation results showed that the power estimates given by both estimation techniques for a hardware component are very close, with a difference that does not exceed 0.3%. This proves that, even when the IP code is not accessible or not modifiable, our approach allows obtaining quite accurate power estimates that early in the design flow thanks to the automation offered by the MDE approach.

International audience; In this paper, we discuss a 3-Dimensional Vehicle Routing Problem (VRP) for a fleet of multi-agents which doing a surveillance mission above a certain terrain. The fleet must performs routes to visit a set of points while respecting constraints. Since VRP is classified as an NP-hard optimization problem, we propose an approximation algorithm to find a best solution to this combinatorial optimization problem. Thus, we select Genetic Algorithm (GA) to answer this challenge. And to boost-up the performance of GA, we decide to add Saving Algorithm (SA) in constructing the initial population. Also, we use Netlogo as the tool for the experiment and simulation as well. The Experimental result shows that GA can be chosen for finding the optimal flyable route in the 3D environment. And it's combination with SA give a very encouraging result in this project.

Nowadays, sorting is an important operation for several real-time embedded applications. It is one of the most commonly studied problems in computer science. It can be considered as an advantage for some applications such as avionic systems and decision support systems because these applications need asorting algorithm for their implementation. However, sorting a big number of elements and/or real-time decision making need high processing speed. Therefore, accelerating sorting algorithms using FPGA can be an attractive solution. In this paper, we propose an efficient hardware implementation for different sorting algorithms (BubbleSort, InsertionSort, SelectionSort, QuickSort, HeapSort, ShellSort, MergeSort and TimSort) from high-level descriptions in the zynq-7000 platform. In addition, we compare the performance of different algorithms in terms of execution time, standard deviationand resource utilization. From the experimental results, we show that the SelectionSort is 1.01-1.23 times faster than other algorithms when N < 64; Otherwise, TimSortis the best algorithm.

International audience

Thèse sous confidentialité du jury jusqu’au 12/10/2015 puis sous embargo illimité de l’auteur.; In this thesis, we propose a scalable and customizable reconfigurable computing platform, with a parallel full-duplex switched communication network, and a software execution model to redefine the computation, communication and reconfiguration paradigms in High Performance Embedded Systems. High Performance Embedded Computing (HPEC) applications are becoming highly sophisticated and resource consuming for three reasons. First, they should capture and process real-time data from several I/O sources in parallel. Second, they should adapt their functionalities according to the application or environment variations within given Size Weight and Power (SWaP) constraints. Third, since they process several parallel I/O sources, applications are often distributed on multiple computing nodes making them highly parallel. Due to the hardware parallelism and I/O bandwidth offered by Field Programmable Gate Arrays (FPGAs), application can be duplicated several times to process parallel I/Os, making Single Program Multiple Data (SPMD) the favorite execution model for designers implementing parallel architectures on FPGAs. Furthermore Dynamic Partial Reconfiguration (DPR) feature allows efficient reuse of limited hardware resources, making FPGA a highly attractive solution for such applications. The problem with current HPEC systems is that, they are usually built to meet the needs of a specific application, i.e., lacks flexibility to upgrade the system or reuse existing hardware resources. On the other hand, applications that run on such hardware architectures are constantly being upgraded. Thus there is a real need for flexible and scalable hardware architectures and parallel execution models in order to easily upgrade the system and reuse hardware resources within acceptable time bounds. Thus these applications face challenges such as obsolescence, hardware redesign cost, sequential and slow reconfiguration, and wastage of computing power.Addressing the challenges described above, we propose an architecture that allows the customization of computing nodes (FPGAs), broadcast of data (I/O, bitstreams) and reconfiguration several or a subset of computing nodes in parallel. The software environment leverages the potential of the hardware switch, to provide support for the SPMD execution model. Finally, in order to demonstrate the benefits of our architecture, we have implemented a scalable distributed secure H.264 encoding application along with several avionic communication protocols for data and control transfers between the nodes. We have used a FMC based high-speed serial Front Panel Data Port (sFPDP) data acquisition protocol to capture, encode and encrypt RAW video streams. The system has been implemented on 3 different FPGAs, respecting the SPMD execution model. In addition, we have also implemented modular I/Os by swapping I/O protocols dynamically when required by the system. We have thus demonstrated a scalable and flexible architecture and a parallel runtime reconfiguration model in order to manage several parallel input video sources. These results represent a conceptual proof of a massively parallel dynamically reconfigurable next generation embedded computers.; Dans cette thèse, nous proposons une architecture reconfigurable scalable et flexible, avec un réseau de communication parallèle « full-duplex switched » ainsi que le modèle d’exécution approprié ce qui nous a permis de redéfinir les paradigmes de calcul, de communication et de reconfiguration dans les systèmes embarqués à haute performance (HPEC). Ces systèmes sont devenus très sophistiqués et consommant des ressources pour trois raisons. Premièrement, ils doivent capturer et traiter des données en temps réel à partir de plusieurs sources d’E/S parallèles. Deuxièmement, ils devraient adapter leurs fonctionnalités selon l’application ou l’environnement. Troisièmement, à cause du parallélisme potentiel des applications, multiples instances de calcul réparties sur plusieurs nœuds sont nécessaires, ce qui rend ces systèmes massivement parallèles. Grace au parallélisme matériel offert par les FPGAs, la logique d’une fonction peut être reproduite plusieurs fois pour traiter des E/S parallèles, faisant du modèle d’exécution « Single Program Multiple Data » (SPMD) un modèle préféré pour les concepteurs d’architectures parallèles sur FPGA. En plus, la fonctionnalité de reconfiguration dynamique est un autre attrait des composants FPGA permettant la réutilisation efficace des ressources matérielles limitées. Le défi avec les systèmes HPEC actuels est qu’ils sont généralement conçus pour répondre à des besoins spécifiques d’une application engendrant l’obsolescence rapide du matériel. Dans cette thèse, nous proposons une architecture qui permet la personnalisation des nœuds de calcul (FPGA), la diffusion des données (E/S, bitstreams) et la reconfiguration de plusieurs nœuds de calcul en parallèle. L’environnement logiciel exploite les attraits du réseau de communication pour implémenter le modèle d’exécution SPMD.Enfin, afin de démontrer les avantages de notre architecture, nous avons mis en place une application d’encodage H.264 sécurisé distribué évolutif avec plusieurs protocoles de communication avioniques pour les données et le contrôle. Nous avons utilisé le protocole « serial Front Panel Data Port (sFPDP) » d’acquisition de données à haute vitesse basé sur le standard FMC pour capturer, encoder et de crypter le flux vidéo. Le système mis en œuvre s’appuie sur 3 FPGA différents, en respectant le modèle d’exécution SPMD. En outre, nous avons également mis en place un système d’E/S modulaire en échangeant des protocoles dynamiquement selon les besoins du système. Nous avons ainsi conçu une architecture évolutive et flexible et un modèle d’exécution parallèle afin de gérer plusieurs sources vidéo d’entrée parallèles.

Thèse sous embargo illimité de l’auteur. Pour les membres de la communauté universitaire (hors UPHF), ce document est accessible via le Prêt entre bibliothèques (s’adresser à votre bibliothèque universitaire).; Security issues are today a key-differentiator in the aviation sector. Indeed, it comes to ensure the safety of expensive equipments but above all to save human lives. In this context, it is necessary to offer an important level of autonomy to helicopters. Although some studies have been carried out in this area, the dynamic generation of a sequence of maneuvers under hard time constraints in an unknown environment still represents a major challenge for many academic and industrial working groups. AIRBUS HELICOPTERS as a leader of helicopters manufacturing, looks forward to integrate an assistance system for mission re-planning in the next generation of aircrafts.The work conducted in this PhD thesis falls within a collaboration between AIRBUS HELICOPTERS and UNIVERSITE DE VALENCIENNES ET DU HAINAUTCAMBRESIS. One of the main purposes of this work is efficient flight plan generation. Indeed, for intelligent assistant systems we need to generate a new path planning inorder to face emergency events such as an equipment failure or adverse weather conditions. The second major objective of this work is the deployment of mission planning tasks onto a high performance architecture CPU/FPGA in order to meet real-time requirements for the dynamic optimization process. In the present work, we first studied efficient flight plan generation. Indeed, we developed efficient and effective algorithms for helicopter path planning. Then, in order to obtain a real-time system, we resolved the problem of scheduling optimization on a heterogeneous architecture CPU / FPGA by proposing several scheduling methods including exact approaches and heuristics.; Les problématiques de sécurité sont aujourd’hui un facteur différentiateur clé dans le secteur aéronautique. Bien que certains systèmes d’assistance aux hélicoptères existent et qu’une partie de la connaissance associée aux situations d’urgence ait pu être identifiée, reste que les travaux antérieurs se limitent pour la plupart à une autonomie de bas niveau. Ainsi la génération d’un plan de vol sous fortes contraintes de temps représente à ce jour une voie d’exploration nouvelle, et un défi technologique essentiel pour l’hélicoptère de demain. A cet égard, AIRBUS HELICOPTERS accorde un fort intérêt à la conception d’un système décisionnel capable de générer des plans de vols en temps réel. L’enjeu de l’intelligence répartie au travers de systèmes décisionnels distribués constitue un axe de recherche fort, et un des contributeurs clés pour un positionnement leader d’AIRBUS HELICOPTERS sur la thématique sécurité. Aujourd’hui, l’étude des systèmes décisionnels embarqués dans les engins volants constitue un défi majeur pour divers groupes de travail académiques et industriels. En effet, la résolution de ce défi fait appel généralement à différentes compétences afin de maîtriser plusieurs aspects du système recouvrant les domaines d’acquisition, d’analyse et de traitement de données. Et ce dans le but de prendre des décisions en temps-réel en prenant en considération plusieurs paramètres contextuels et environnementaux. Les défis scientifiques à contourner dans la présente thèse s’articulent sur deux axes majeurs. Dans un premier temps, il faut proposer une approche complète pour une planification en temps réel d’un plan de vol d’hélicoptères. Permettant à cette dernière de faire face à d’éventuels événements dynamiques tel que l’apparition de nouveaux obstacles ou un changement de mission. Ensuite, nous nous intéressons à une implantation embarquée de la solution proposée sur une architecture hétérogène haute performance.