1. A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology
- Author
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Norifumi Kajimura, H. Otake, F. Ito, Kazushige Kanda, Y. Okukawa, Teruhiko Kamei, Mitsuhiro Noguchi, M. Higashitani, M. Kojima, Masahiro Yoshihara, Kazuhide Yoneya, Frank Tsai, Masanobu Shirakawa, M. Itoh, Siu Lung Chan, Toshiki Hisada, Yosuke Kato, Takashi Taira, Eiichi Makino, Binh Quang Le, Dai Nakamura, G. Hemink, Toshio Yamamura, Alex Mak, Shinji Miyamoto, Raul-Adrian Cernea, Yoshinao Suzuki, Shigeo Ohshima, Susumu Fujimura, Koji Hosono, Toru Miwa, Yoshiaki Takeuchi, T. Maruyama, T. Arizono, Toshitake Yaegashi, Masaru Koyanagi, and K. Ino
- Subjects
Engineering ,Hardware_MEMORYSTRUCTURES ,business.industry ,Nand flash memory ,% area reduction ,NAND gate ,CMOS ,Hardware_GENERAL ,Charge trap flash ,business ,Computer hardware ,Gate equivalent ,Leakage (electronics) ,Voltage - Abstract
NAND flash memory use in digital still cameras and cellular phones is driving demand for larger-capacity storage. Moreover, NAND flash has the potential to replace HDDs. To achieve larger capacity while maintaining low cost per bit, technical improvements in feature size and area reduction are essential. To meet the stringent requirements, we develop a 16 Gb 4-level NAND flash memory in 43 nm CMOS technology. In 43 nm generation, gate-induced drain leakage (GIDL) influences the electrical field on both sides of NAND strings. GIDL causes severe program disturb problems to NAND flash memories. To avoid GIDL, two dummy wordlines (WL) on both sides of NAND strings are added. This is effective because the dummy gate voltages, are selected independent of the program inhibit voltage.
- Published
- 2008
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