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Modern SoCs require increasingly complex embedded control deep within their numerous sub-blocks without adding significant die area. This motivated the creation of $\mu $ RTL, a novel toolset for systematically designing efficient pipelined implementations of embedded instruction sets originally intended for multicycle execution. $\mu $ RTL utilizes hardwired micro-op translation, a technique commonly used in the instruction decoders of large super-scalar microprocessors, however this technique has been overlooked for designing smaller, more efficient embedded microprocessors. Furthermore, the tools to develop instruction decoders with micro-op translation are proprietary and the techniques are trade secrets. The $\mu $ RTL toolset is open-source and this letter clearly presents the methodology. The methodology emphasizes direct opcode decoding from multiple synthesized Verilog blocks versus traditional microprogramming which uses sequential decoding from a ROM. Our results show that a pipelined $\mu $ RTL microarchitecture achieves a 21.8% reduction in size compared to a hardwired multicycle implementation of the same instruction set. Additionally, the performance of 0.75 DMIPS/MHz surpasses the RISC-V PicoRV32 by 44.2% and the AVR RISC by 82.9%. These improvements in performance, power, and area are of interest to embedded system architects. [ABSTRACT FROM AUTHOR]

Low density parity check code (LDPC) is the most popular error correction code (ECC) for current nand flash memory controllers. Next generation flash memory, such as triple-level cell (TLC) and quad-level cell (QLC) with a higher bit error rate, bring up the demand for superior ECC algorithms providing excellent performance and acceptable hardware overhead. This letter proposes turbo product code (TPC) as an alternative to LDPC by exploring embedding of a TPC engine into a solid-state drive (SSD) controller architecture. The implementation of this TPC engine uses 2-D error coding and applies the Bose-Chaudhuri–Hocquenghem (BCH) code in each dimension. The algorithm is further improved by flipping the dedicated bit matrix when the basic TPC decoding algorithm terminates with uncorrectable conditions. This bit-flipping enhanced TPC (BFE-TPC) module is finally integrated into a nonvolatile memory express (NVMe) SSD controller driving eight flash memory channels. This BFE-TPC module illustrates the potential of 2D-TPCs as a replacement for LDPCs due to its high throughput and low hardware overhead. [ABSTRACT FROM AUTHOR]

In computer-numerical-controlled (CNC) machine tools, factors affecting machining precision mainly stem from the machine's own geometric errors and errors occurring during cutting due to thermal effects on its structure. Typically, thermal errors contribute to more than 70% of the total error. Hence, minimizing thermal errors in CNC machine tools is highly regarded. One significant and commonly used approach is the thermal error compensation (TEC) method. Although the TEC method has been extensively applied in both laboratory and industrial CNC machines, several challenges remain. For instance, the determination of optimal temperature characteristic points for various CNC machine tools requires improved methods, the mathematical models for predicting and compensating thermal errors are not sufficiently accurate, and there is poor compensation performance under varying cutting conditions. In this research, we focus on thermal error prediction and compensation technology for a CNC highspeed four-rail vertical machining center. Through actual cutting experiments, we measure temperatures at feature points on the machine and spindle deformation using various high-tech sensors. Subsequently, precise prediction and rapid compensation models for thermal errors are established using support vector regression and transfer function matrix methods, respectively. Finally, a TEC system based on a single-chip microprocessor is developed. In this system, we perform real-time TEC during actual machining by adjusting the machine's original point drift. Results from actual cutting experiments demonstrate that the developed TEC system can effectively reduce the target machine's thermal deformation from 110 µm to within 10 µm in real time. [ABSTRACT FROM AUTHOR]

MicroRNA (miRNA) biogenesis is initiated upon cleavage of a primary miRNA (pri-miRNA) hairpin by the Microprocessor (MP), composed of the Drosha RNase III enzyme and its partner DGCR8. Multiple pri-miRNA sequence motifs affect MP recognition, fidelity, and efficiency. Here, we performed cryoelectron microscopy (cryo-EM) and biochemical studies of several let-7 family pri-miRNAs in complex with human MP. We show that MP has the structural plasticity to accommodate a range of pri-miRNAs. These structures revealed key features of the 5′ UG sequence motif, more comprehensively represented as the "flipped U with paired N" (fUN) motif. Our analysis explains how cleavage of class-II pri-let-7 members harboring a bulged nucleotide generates a non-canonical precursor with a 1-nt 3′ overhang. Finally, the MP-SRSF3-pri-let-7f1 structure reveals how SRSF3 contributes to MP fidelity by interacting with the CNNC motif and Drosha's Piwi/Argonaute/Zwille (PAZ)-like domain. Overall, this study sheds light on the mechanisms for flexible recognition, accurate cleavage, and regulated processing of different pri-miRNAs by MP. [Display omitted] • The Microprocessor has the plasticity for accommodating a diversity of pri-miRNAs • RNA drives Microprocessor domain repositioning for pri-let-7 cleavage • The UG motif is redefined as a fUN motif for a comprehensive pri-miRNA classification • SRSF3 assists Drosha by positioning it at the basal junction of the pri-miRNA Garg et al. used cryo-EM to determine several structures of different pri-let-7 pri-miRNAs in complex with the Microprocessor, highlighting structural features important for flexible recognition, pri-miRNA cleavage, and cleavage regulation. The fUN structural motif and CNNC-SRSF3-assisted Drosha loading present insights applicable to the processing of hundreds of pri-miRNAs. [ABSTRACT FROM AUTHOR]

Chua's circuit represents a paradigm for nonlinear dynamics and chaos in electronic circuits. In this paper, its discrete-time counterpart is considered showing the occurrence of nonlinear resonance when driven by an external sinusoidal input. Evidences of jump resonance are revealed from several regions of the parameter space. An approach based on quasi-analytic methods, numerical simulations and several experiments with digital microprocessors is presented, further confirming the richness of Chua's circuit dynamical behavior. The high selectivity of the jump resonance observed from the discrete-time Chua's circuit paves the way for the implementation of low-cost high-resolution frequency drift sensing devices. [ABSTRACT FROM AUTHOR]

Wearable devices have generally been rigid due to their reliance on silicon‐based technologies, while future wearables will utilize flexible components for example transistors within microprocessors to manage data. Two‐dimensional (2D) semiconducting flakes have yet to be investigated in fiber transistors but can offer a route toward high‐mobility, biocompatible, and flexible fiber‐based devices. Here, the electrochemical exfoliation of semiconducting 2D flakes of tungsten diselenide (WSe2) and molybdenum disulfide (MoS2) is shown to achieve homogeneous coatings onto the surface of polyester fibers. The high aspect ratio (>100) of the flake yields aligned and conformal flake‐to‐flake junctions on polyester fibers enabling transistors with mobilities μ ≈1 cm2 V−1 s−1 and a current on/off ratio, Ion/Ioff ≈102–104. Furthermore, the cytotoxic effects of the MoS2 and WSe2 flakes with human keratinocyte cells are investigated and found to be biocompatible. As an additional step, a unique transistor 'knot' architecture is created by leveraging the fiber diameter to establish the length of the transistor channel, facilitating a route to scale down transistor channel dimensions (≈100 µm) and utilize it to make a MoS2 fiber transistor with a human hair that achieves mobilities as high as μ ≈15 cm2 V−1 s−1. [ABSTRACT FROM AUTHOR]

Persistent security challenges in Industry 4.0 due to the limited resources of IoT devices necessitate innovative solutions. Addressing this, this study introduces the ASCON algorithm for lightweight authenticated encryption with associated data, enhancing confidentiality, integrity, and authenticity within IoT limitations. By integrating Digital Twins, the framework emphasizes the need for robust security in Industry 4.0, with ASCON ensuring secure data transmission and bolstering system resilience against cyber threats. Practical validation using the MQTT protocol confirms ASCON's efficacy over AES-GCM, highlighting its potential for enhanced security in Industry 4.0. Future research should focus on optimizing ASCON for microprocessors and developing secure remote access tailored to resource-constrained devices, ensuring adaptability in the digital era. [ABSTRACT FROM AUTHOR]

In the present paper, the use of programmable microprocessors to develop a computerized stand for the preparation of a mixture of flammable/toxic/explosive gases in order to obtain mixtures at concentrations in explosive range is presented. The operating principle of the stand is based on the mixing of two volumetric flows, controlled with the help of microprocessors, where gases are stored and circulated at atmospheric pressure through cylindrical injectors, driven by stepper motors so that the gas circuit does not require valves. The exit of the stand is a homogenization chamber, with agitator and sensor to confirm the desired concentration of the mixture. This automated stand eliminates mechanical, electric or pneumatic valves from the gas circuits, avoiding elements with high mechanical resistance suitable for high pressures/depressions, removing the possibility of the return of the gas flow, without sensitivity to sudden pressures variations. [ABSTRACT FROM AUTHOR]

Wireless medical telemetry systems (WMTSs) are typical radio communication–based medical devices that monitor various biological parameters, such as electrocardiograms and respiration rates. In Japan, the assigned frequency band for WMTSs is 400 MHz. However, the issues accounting for poor reception in WMTS constitute major concerns. In this study, we analyzed the effects of electromagnetic interferences (EMIs) caused by other radio communication systems, the intermodulation (IM) effect, and noises generated from electrical devices on WMTS and discussed their management. The 400-MHz frequency band is also shared by other radio communication systems. We showed the instantaneous and impulsive voltages generated from the location-detection system for wandering patients and their potential to exhibit EMI effects on WMTS. Further, we presented the IM effect significantly reduces reception in WMTS. Additionally, the electromagnetic noises generated from electrical devices, such as light-emitting diode lamps and security cameras, can exceed the 400 MHz frequency band as these devices employ the switched-mode power supply and/or central processing unit and radiate wideband emissions. Moreover, we proposed and evaluated simple and facile methods using a simplified spectrum analysis function installed in the WMTS receiver and software-defined radio for evaluating the electromagnetic environment. [ABSTRACT FROM AUTHOR]

Collecting data such vibration signal or others from elevators is crucial for a regular maintenance or emergency repair in industry. However, traditional methods for data transmission through compression and decompression process usually require large input data arrays to be assigned. Therefore, a long computational time is unavoidable so that it may affect system performance efficiency significantly. Therefore, an elevator vibration and loading data collection system was developed using simple compression encoding mechanism. First, in Data Acquisition Unit, the signal-acquiring microprocessor is used for data acquisition through Inter-Integrated Circuit (I2C) bus. Second, in Data Storage Unit, the collected data from the signal-acquiring microprocessor is compressed and transmitted to the signal-processing microprocessor. Third, in Monitor Unit, the elevator analysis tool is developed to analyze the vibration data, which can be viewed directly from APP. Experimental results demonstrated that the restored data are consistent with the results measured from the standard instrument. The proposed hexadecimal compression process can make the data transmission mechanism simple, but two times faster than that using traditional way without compression. Consequently, the demanded memory capacity for signal transmission can be therefore reduced considerably. [ABSTRACT FROM AUTHOR]

As microprocessor currents exceed 500 A and slew rate reaches 1000 A/µs, increasing the decoupling capacitance on the motherboard to ensure normal operation of the microprocessor is inevitable because of the limited response capability of the voltage regulator. However, the area of the motherboard used for capacitors is usually narrow. To reduce the required capacitance, a novel buck converter with an auxiliary circuit for charge compensation using switched capacitors is proposed. The auxiliary circuit is not activated during the steady state. When the load current changes rapidly, the switched capacitors can quickly absorb or release charge to suppress voltage fluctuations. A 12 V–0.9 V buck converter has been built and tested under a 480 A load current step and a 960 A/µs current slew rate. The proposed scheme with 9.964 mF capacitance has an overshoot of 115 mV and an undershoot of 89 mV. Compared with the conventional PID scheme, the proposed scheme can save 58.4% of the capacitance for the same voltage fluctuations or suppress 39.5% of overshoot and 37.3% of undershoot with the same capacitance. [ABSTRACT FROM AUTHOR]

In response to the problem of disturbance in the imaging equipment of stratospheric airships, this study designs a vibration isolation and stability system for carrying imaging equipment. The system mainly consists of microprocessor, gimbal, voice coil motor (VCM) and rubber ring. By using adaptive control law based on characteristic model to control the double closed control loop of the motor composed of position loop and speed loop, the camera deflection caused by disturbance is effectively eliminated. Furthermore, in vertical vibration suppression, the adaptive control law based on the characteristic model is also applied to the double closed control loop of the voice coil motor, which removes most of the vertical vibration and realizes active vibration isolation. The passive isolation of the system is completed by rubber rings. The experimental results show that the vibration isolation and stabilization system have good performance in complex disturbance environments, effectively stabilizing the imaging equipment. [ABSTRACT FROM AUTHOR]

With the advancement in artificial intelligence technology, autonomous mobile robots have been utilized in various applications. In autonomous driving scenarios, object classification is essential for robot navigation. To perform this task, light detection and ranging (LiDAR) sensors, which can obtain depth and height information and have higher resolution than radio detection and ranging (radar) sensors, are preferred over camera sensors. The pillar-based method employs a pillar feature encoder (PFE) to encode 3D LiDAR point clouds into 2D images, enabling high-speed inference using 2D convolutional neural networks. Although the pillar-based method is employed to ensure real-time responsiveness of autonomous driving systems, research on accelerating the PFE is not actively being conducted, although the PFE consumes a significant amount of computation time within the system. Therefore, this paper proposes a PFE hardware accelerator and pillar-based object classification model for autonomous mobile robots. The proposed object classification model was trained and tested using 2971 datasets comprising eight classes, achieving a classification accuracy of 94.3%. The PFE hardware accelerator was implemented in a field-programmable gate array (FPGA) through a register-transfer level design, which achieved a 40 times speedup compared with the firmware for the ARM Cortex-A53 microprocessor unit; the object classification network was implemented in the FPGA using the FINN framework. By integrating the PFE and object classification network, we implemented a real-time pillar-based object classification acceleration system on an FPGA with a latency of 6.41 ms. [ABSTRACT FROM AUTHOR]

Although molecular vibronic spectra generation is pivotal for chemical analysis, tackling such exponentially complex tasks on classical computers remains inefficient. Quantum simulation, though theoretically promising, faces technological challenges in experimentally extracting vibronic spectra for molecules with multiple modes. Here, we propose a nontrivial algorithm to generate the vibronic spectra using states with zero displacements (squeezed vacuum states) coupled to a linear optical network, offering ease of experimental implementation. We also fabricate an integrated quantum photonic microprocessor chip as a versatile simulation platform containing 16 modes of single-mode squeezed vacuum states and a fully programmable interferometer network. Molecular vibronic spectra of formic acid and thymine under the Condon approximation are simulated using the quantum microprocessor chip with high reconstructed fidelity (> 92%). Furthermore, vibronic spectra of naphthalene, phenanthrene, and benzene under the non-Condon approximation are also experimentally simulated. Such demonstrations could pave the way for solving complicated quantum chemistry problems involving vibronic spectra and computational tasks beyond the reach of classical computers. Proof-of-principle photonic quantum simulations of molecular vibronic spectra have been realised, but scalability to more complex systems is hindered by the difficulties in generating squeezed coherent states with multiple modes. Here, the authors demonstrate an alternative approach relying on vacuum-squeezed state. [ABSTRACT FROM AUTHOR]

This study aimed to apply a microprocessor on a wireless automated vehicle to achieve real-time tracking of moving objects. The targets captured by the camera on the vehicle were first separated from their background through background subtraction. Next, morphological processing was performed to remove unnecessary information. An enhanced seeded region growing method was used to achieve image segmentation by labeling and segmenting the targets effectively, thus enhancing the accuracy and resolving the problem of object concealment. The corresponding red, green, and blue colors of each target were calculated through a color space, which was then converted into an enhanced luminance/chroma blue/chroma red (YUV) color space for color histogram modeling and storage, so as to increase the system's tracking speed. The enhanced YUV colors also achieved accurate tracking in dark places. After inputting the next image, an enhanced agglomerative hierarchical clustering method was used to agglomerate and connect pixels with the same YUV for tracking. A proportional-integral-derivative controller controlled the motors on the camera lens and the vehicle so that the target could be tracked properly in real-time. The experimental results revealed that our proposed tracking method performed better than conventional tracking methods. [ABSTRACT FROM AUTHOR]

This work is an original contribution consisting in the implementation and evaluation of a selective value predictor in a multicore environment, with focus on long latency arithmetical instructions, having the goal to break the dataflow bottleneck of each core, thus increasing the overall performance. The Sniper simulator was used to augment the Intel Nehalem architecture with a value predictor and to estimate the computing performance, area of integration, power consumption, energy efficiency and chip temperature for the enhanced architecture. We run simulations and study the impact of the number of values which are used for prediction for each instruction. By increasing the history length, we measured on average more than 3 % increase in performance (core speed-up), a reduction in chip temperature from 57.8 C to 56.17 C, and lower energy consumption in most cases compared with the baseline configuration. We also realized a comparison between the value prediction and dynamic instruction reuse techniques in equitable condition (to exploit the same value locality), where we highlight the advantages and disadvantages of each technique in the given context.

In this article, we introduce parallelproj, a novel open-source framework designed for efficient parallel computation of projections in tomography leveraging either multiple CPU cores or GPUs. This framework efficiently implements forward and back projection functions for both sinogram and listmode data, utilizing Joseph's method, which is further extended to encompass time-of-flight (TOF) PET projections. Our evaluation involves a series of tests focusing on PET image reconstruction using data sourced from a state-of-the-art clinical PET/CT system. We thoroughly benchmark the performance of the projectors in non-TOF and TOF, sinogram, and listmode employing multi CPU-cores, hybrid CPU/GPU, and exclusive GPU mode. Moreover, we also investigate the timing of non-TOF sinogram projections calculated in STIR (Software for Tomographic Image Reconstruction) which recently integrated parallelproj as one of its projection backends. Our results indicate that the exclusive GPU mode provides acceleration factors between 25 and 68 relative to the multi-CPUcore mode. Furthermore, we demonstrate that OSEM listmode reconstruction of state-of-the-art real-world PET data sets is achievable within a few seconds using a single consumer GPU. [ABSTRACT FROM AUTHOR]

In the face of rising population, erratic climate, resource depletion, and increased exposure to natural hazards, environmental monitoring is increasingly important. Satellite data form most of our observations of Earth. On-the-ground observations based on in situ sensor systems are crucial for these remote measurements to be dependable. Providing open-source options to rapidly prototype environmental datalogging systems allows quick advancement of research and monitoring programs. This paper introduces Loom, a development environment for low-power Arduino-programmable microcontrollers. Loom accommodates a range of integrated components including sensors, various datalogging formats, internet connectivity (including Wi-Fi and 4G Long Term Evolution (LTE)), radio telemetry, timing mechanisms, debugging information, and power conservation functions. Additionally, Loom includes unique applications for science, technology, engineering, and mathematics (STEM) education. By establishing modular, reconfigurable, and extensible functionality across components, Loom reduces development time for prototyping new systems. Bug fixes and optimizations achieved in one project benefit all projects that use Loom, enhancing efficiency. Although not a one-size-fits-all solution, this approach has empowered a small group of developers to support larger multidisciplinary teams designing diverse environmental sensing applications for water, soil, atmosphere, agriculture, environmental hazards, scientific monitoring, and education. This paper not only outlines the system design but also discusses alternative approaches explored and key decision points in Loom's development. [ABSTRACT FROM AUTHOR]

Recent evaluations of counter-based periodic testing strategies for fault detection in Microprocessor (μP) have shown that only a small set of counters is needed to provide complete coverage of severe faults. Severe faults are defined as faults that leak sensitive information, e.g., an encryption key on the output of a serial port. Alternatively, fault detection can be accomplished by executing instructions that periodically test the control and functional units of the μP. In this paper, we propose a fault detection method that utilizes an 'engineered' executable program combined with a small set of strategically placed counters in pursuit of a hardware Periodic Built-In-Self-Test (PBIST). We analyze two distinct methods for generating such a binary; the first uses an Automatic Test Generation Pattern (ATPG)-based methodology, and the second uses a process whereby existing counter-based node-monitoring infrastructure is utilized. We show that complete fault coverage of all leakage faults is possible using relatively small binaries with low latency to fault detection and by utilizing only a few strategically placed counters in the μP. [ABSTRACT FROM AUTHOR]

The digital pulse processing unit is the main part of a digital gamma spectrometer. There has been recent interest in implementing this unit using microcontroller chips rather than FPGA chips. In this paper, we aim to implement a digital pulse processing unit using a Cortex-M4-based microcontroller. The Cortex-M4 microprocessor features DSP capabilities. The proposed design is tested using a sodium iodide detector. It achieves acceptable energy resolution at moderate input count rates. The proposed design in this paper achieves a four times higher throughput than the throughput achieved by our previously proposed Cortex-M3-based design. [ABSTRACT FROM AUTHOR]

This paper presents the experimental results of nMOS quantum dot gate field-effect transistor (QDG-FET) based four-state inverter fabricated and tested with Si/SiO2 and Ge/GeO2 quantum dots. The site-specific self-assembly of SiOx-cladded Si and GeOx-cladded Ge quantum dot layers in the gate region implements both the driver and load FETs in enhancement nMOS inverters. A four-state inverter will allow the reduction of FET count in logic block in microprocessors. [ABSTRACT FROM AUTHOR]

This paper aims to design an Android interface, an Arduino bot, and write a program on the Arduino microprocessor. Arduino cars contain Arduino microcontrollers with basic mobility features. Arduino programs contain instructions for mediating between an Android controller and an Arduino car. Android mobile controllers use different mobile sensors to supervise motion. An appropriate program in the Arduino microprocessor to interact with the Android controller has to be created. The program has been successfully compiled through the Arduino IDE on the Arduino microprocessor and loaded into it after proper checking of the logic to decrease any loss or damage to the hardware. An Android application is created that provides the user with an interface to interact with the Arduino-powered car. The interface is easy to use and provides feedback from the Arduino microprocessor through Bluetooth after giving instructions to the Arduino for various actions through the interface. The Android application is to be created with the help of Android Studio, which provides more capability and stability. After doing all of this, the application is thoroughly tested, and the maximum number of errors and wrong logic in the microprocessor program are found. [ABSTRACT FROM AUTHOR]

This letter proposes three novel substitution box (S-box) architectures for lightweight block ciphers. The proposed S-box architectures are based on the Boolean decomposition to achieve the design tradeoffs. Absorption of the Terminal Nodes property, positive Davio expansion, and Shannon decomposition are explored for the three S-box architectures. The proposed S-box variants are included in the SPN layer of the Midori-64 block cipher to validate their utility for a lightweight cipher. Also, to demonstrate the generality of the proposed logic decomposition approaches, the proposed work is expanded to the composite field architectures for the S-box of AES-128. Compared with state-of-the-art designs, the proposed designs exhibit a reduction of 66%, 36%, and 21% for energy, delay, and power metrics. [ABSTRACT FROM AUTHOR]

Introduction: Bilateral microprocessor-controlled prosthetic knee (MPK) users have unique needs in traversing environmental barriers compared to unilateral users. An enhancement to the GeniumTM/Genium X3TM MPK which included an updated ruleset, hydraulics, and new bilateral parameter presets was made to improve safety while stumbling and the smoothness of gait for all users while also improving the experience of bilateral users. The purpose of the study was to evaluate the effectiveness of the enhancements in a sample with unilateral and bilateral amputation. Methods: A convenience sample of MPK users was recruited from two sites in the USA in two phases. Assessments included the L-Test of Functional Mobility, Activity-specific Balance Confidence Scale, Prosthetic Limb User Survey of Mobility, a study-specific questionnaire, and the Comparative Activities of Daily Living (ADL) Questionnaire. Statistical significance of extracted data was tested with the Wilcoxon Rank-Sum Test for independent data and Wilcoxon Signed-Rank for paired data with an a priori significance level of p < 0.05. Unilateral subjects were age-matched to the group of bilateral subjects for between-groups and within-groups analyses. Results: Twenty-six subjects (n = 26) were enrolled. Stumble frequency reduced 85% from 16.0 ± 39.7 to 2.4 ± 2.3 (p = 0.008) between baseline and final assessment overall. The bilateral group reported 50% (p = 0.009) and 57% (p = 0.009) greater relative improvement in patient-reported ease and safety, respectively, of completing ADLs compared to the unilateral group. The unilateral group reported residual limb pain and low back pain reduced from 2.3 to 1.4 (p = 0.020) and 3.8 to 1.8 (p = 0.027), respectively, whereas the bilateral group did not. Discussion: Substantial reductions in stumbles, residual limb pain, and back pain were shown overall. These reductions were driven by the unilateral group who also showed improvements in comfort, exertion, and concentration while walking. The enhancements to the knee likely reduced some gait asymmetry for unilateral users. Improvements in patient-reported ease and safety of completing ADLs were shown overall and were driven by the bilateral group. This study shows further improvement in patient experience is achievable through innovation in MPK technology even for patients who appear to be functioning well. [ABSTRACT FROM AUTHOR]

Transforming current complementary metal–oxide–semiconductor (CMOS) technology to fabricate memory chips and microprocessors into environmentally friendlier electronics requires the development of new approaches to resource- and energy-efficient electron transport and switching materials. Metal and multi-metal oxide layers play a key role in high-end technical applications. However, these layers are commonly produced through high-energy and high-temperature procedures. Herein, we demonstrate our first attempts to obtain stimuli-responsive mixed-metal oxide thin films from solution-processed molecular precursors under milder conditions. The molecular compounds of interest were prepared by one-pot reactions of a CoII carboxylate complex, triethylamine (Et3N), N-butyldiethanolamine (H2bda), and a hexanuclear complex [Ce6O4(OH)4(piv)12] (Hpiv = pivalic acid) or [Zr6O4(OH)4(ib)12(H2O)]·3Hib (Hib = isobutyric acid) in acetonitrile solution. The resulting charge-neutral, heterometallic coordination compounds display a ligand-supported pentanuclear {Ce IV3 Co III2 } core (in 1) and a dodecanuclear {Zr IV6 Co II6 } core (in 2), exhibiting thermal stability up to ca. 100 °C in air. Compound 2 was deposited and analyzed on Au(111) and SiO2/Si(100) surfaces to explore its potential as a single-molecule precursor for the preparation of atomically precise, complex mixed-metal oxide thin films. The adsorption characteristics of it demonstrate the ability to form stable agglomerates on the investigated surfaces. [ABSTRACT FROM AUTHOR]

The microprocessor without interlocked piped stages (MIPS) and LoongArch are reduced instruction set computing (RISC) processor architectures, which have advantages in terms of energy consumption and efficiency. There are few studies on the application of MIPS and LoongArch central processing units (CPUs) in geoscientific numerical models. In this study, the Loongson 3A4000 CPU platform with the MIPS64 architecture and the Loongson 3A6000 CPU platform with the LoongArch architecture were used to establish the runtime environment for the air quality modelling system Weather Research and Forecasting–Comprehensive Air Quality Model with extensions (WRF-CAMx) in the Beijing–Tianjin–Hebei region. The results show that the relative errors for the major species (NO 2 , SO 2 , O 3 , CO, PNO 3 , and PSO 4) between the MIPS and X86 benchmark platforms are within ± 0.1 %. The maximum mean absolute error (MAE) of major species ranged up to 10 -2 ppbV or µ g m -3 , the maximum root mean square error (RMSE) ranged up to 10 -1 ppbV or µ g m -3 , and the mean absolute percentage error (MAPE) remained within 0.5 %. The CAMx takes about 195 min on the Loongson 3A4000 CPU, 71 min on the Loongson 3A6000 CPU, and 66 min on the Intel Xeon E5-2697 v4 CPU, when simulating a 24 h case with four parallel processes using MPICH. As a result, the single-core computing capability of the Loongson 3A4000 CPU for the WRF-CAMx modelling system is about one-third of the Intel Xeon E5-2697 v4 CPU, and the one of Loongson 3A6000 CPU is slightly lower than that of Intel Xeon E5-2697 v4 CPU; but, the thermal design power (TDP) of Loongson 3A4000 is 40 W, while the TDP of Loongson 3A6000 is 38 W, only about one-fourth of that of Intel Xeon E5-2697 v4, whose TDP is 145 W. The results also verify the feasibility of cross-platform porting and the scientific usability of the ported model. This study provides a technical foundation for the porting and optimization of numerical models based on MIPS, LoongArch, or other RISC platforms. [ABSTRACT FROM AUTHOR]

Embedded computers are ubiquitous in products across various industries, including the automotive and medical industries, and in consumer goods such as appliances and entertainment devices. These specialized computing systems utilize Systems on Chips (SoCs), devices that are made up of one or more main microprocessor cores. SoCs are augmented with sub-blocks that perform dedicated tasks to support the system. Sub-blocks contain custom logic or small-footprint microprocessors, depending upon their complexity, and perform support functions such as clock generation, device testing, phase-locked loop synchronization and peripheral management for interfaces such as a Universal Serial Bus (USB) or Serial Peripheral Interface (SPI). SoC designers have traditionally obtained sub-blocks from commercial vendors. While these sub-blocks have well-defined interfaces, their internal implementations are opaque. Without visibility of the specifics of the implementation, SoC designers are limited to the degree to which they can optimize these off-the-shelf sub-blocks. The result is that power and area constraints are dictated by the design of a third-party vendor. This work introduces a novel idea: using an open-source, small, multitasking, real-time operating system inside an SoC sub-block to manage multiple processes, thereby conserving code space. This OS is TurbOS, a new operating system whose primary goal is to provide the highest performance using the least amount of space. It is written in the assembly language of a new pipelined 16-bit microprocessor developed at the University of Florida, the Turbo9. TurbOS is derived from and incorporates the design benefits of an existing operating system called NitrOS-9, and reduces the code size from its progenitor by nearly 20%. Furthermore, it is over 80% smaller than the popular FreeRTOS operating system. TurbOS delivers a rich feature set for managing memory and process resources that are useful in SoC sub-block applications in an extremely small footprint of only 3 kilobytes. [ABSTRACT FROM AUTHOR]

In predictive control of induction motors, control signals are adjusted by predicting the future behavior of the motor. These predictions are made on important parameters such as motor speed, current, and torque, and are supported by real-time data. In general, in model predictive control (MPC) method, the input and output of the system are optimized using cost functions based on reference values. Although the induction motor operates in continuous time, discretization methods are needed for performing the necessary current switching and feedback control with microprocessors. For reference speed tracking in this study, the stator current of a three-phase induction motor with specifications of 60 Hz, 50 HP, and 460 V was decomposed for the first time using Crank–Nicholson, Verlet integration, and Runge– Kutta Ralston methods, which are finite control set (FCS)-MPC discretization methods. In this paper, we compared the Forward Euler, Runge–Kutta 4, Runge–Kutta Ralston, Taylor series, Crank–Nicolson, and Verlet integration techniques, which are FCS-MPC methods, with the conventional discrete-time indirect field oriented control (IFOC) method for speed control of induction motors. Based on the simulation data obtained from the induction motor, overshoot, settling time, reference speed root mean square value, and total harmonic distortion values were taken into account. The Verlet integration method had the least settling time than other methods, in the range of 0–4 s, including nominal speed transitions. When the response signals were examined, it was seen that the Verlet integration method gave the lowest settling time and overshoot percentage values for the 4–8 s, while the Forward Euler method gave the lowest settling time and overshoot percentage values for the 8–10 s. [ABSTRACT FROM AUTHOR]

As United States healthcare transitions from traditional fee-for-service models to value-based care, there is increased need to demonstrate quality care through clinical outcomes. Therefore, the purpose of this study was to create equations to calculate an expected mobility score for lower limb prosthesis users specific to their age, etiology, and amputation level to provide benchmarks to qualify good outcomes. A retrospective cross-sectional analysis of outcomes collected during clinical care was performed. Individuals were grouped based on amputation level (unilateral above-knee (AKA) or below-knee (BKA)) and etiology (trauma or diabetes/dysvascular (DV)). The mean mobility score (PLUS-M® T-score) for each year of age was calculated. AKAs were further stratified into having a microprocessor knee (MPK) or non-microprocessor (nMPK) for secondary analysis. As expected, average prosthetic mobility declined with age. Overall, BKAs had higher PLUS-M T-scores compared to AKAs and trauma etiologies had higher scores compared to DV. For AKAs, those with a MPK had higher T-scores compared to those with a nMPK. Results from this study provide average mobility for adult patients across every year of life. This can be leveraged to create a mobility adjustment factor to qualify good outcomes in lower limb prosthetic care. Normative values of mobility are needed to qualify good outcomes in prosthetic care as healthcare shifts towards value-based care. Understanding where an individual is relative to others with similar characteristics (e.g., age, etiology, gender, amputation level, and device type) can provide clinicians with better benchmarks for individual goal-setting. The ability to generate predicted mobility scores specific to each individual can create a mobility adjustment factor to better qualify good outcomes. [ABSTRACT FROM AUTHOR]

The General Court's annulment of the European Commission's finding that Intel's conditional rebate scheme was abusive underscores the Court's readiness to scrutinize in detail the economic analysis, including the as-efficient competitor (AEC) test. This paper critically reviews some of the key errors that the Commission, according to the Court, made in relation to the implementation of that test, focusing on some of its main ingredients, namely the contestable share of the market, the conditional portion of the rebates, and the relevant cost benchmark. We conclude that the Court's assessment provides useful lessons for how to perform thorough and robust economic analysis not only within the context of an AEC test but in competition cases more generally. At the same time, considering the test's intrinsic limitations, we find that, aside from the test's implementation, its informative value should also be explored, based on economic theory and the facts of the case. [ABSTRACT FROM AUTHOR]

This study establishes thermodynamic assumptions regarding the growth of condensation droplets and a mathematical formulation of droplet energy functionals. A model of the gas–liquid interface condensation rate based on kinetic theory is derived to clarify the relationship between condensation conditions and intermediate variables. The energy functional of a droplet, derived using the principle of least action, partially elucidates the inherent self-organizing growth laws of condensed droplets, enabling predictive modeling of the droplet's growth. Considering the effects of the condensation environment and droplet heat transfer mechanisms on droplet growth dynamics, we divide the process into three distinct stages, marked by critical thresholds of 105 nm3 and 1010 nm3. Our model effectively explains why the observed contact angle fails to reach the expected Wenzel contact angle. This research presents a detailed analysis of the factors affecting surface condensation and heat transfer. The predictions of our model have an error rate of less than 3% error compared to baseline experiments. Consequently, these insights can significantly contribute to and improve the design of condensation heat transfer surfaces for the phase-change heat sinks in microprocessor chips. [ABSTRACT FROM AUTHOR]

Induction motors (IM) play a fundamental role in the industrial sector because they are robust, efficient, and low-cost machines. Changes in the environment, installation errors, or modifications to working conditions can generate faults in induction motors. The trend on IM fault detection is focused on the design techniques and sensors capable of evaluating multiple faults with various signals using non-invasive analysis. The methodology is based on processing electric current signals by applying the short-time Fourier transform (STFT). Additionally, the computation of the mean and standard deviation of infrared thermograms is proposed as main indicators. The proposed system combines both parameters by means of Support Vector Machine and k-nearest-neighbor classifiers. The development of the diagnostic system was done with digital hardware implementations using a Xilinx PYNQ Z2 card that integrates an FPGA with a microprocessor, thus taking advantage of the acquisition and processing of digital signals and images in hardware. The proposed method has proved to be effective for the classification of healthy (HLT), misalignment (MAMT), unbalance (UNB), damaged bearing (BDF), and broken rotor bar (BRB) faults with an accuracy close to 99%. [ABSTRACT FROM AUTHOR]

This paper presents an innovative approach for error prediction (EP) tailored to near-threshold operations, addressing the energy-efficient requirements of digital circuits in applications such as IoT devices and wearables. The novel EP technique combines the benefits of error prediction and detection, effectively addressing critical issues associated with each method by enabling adaptive prediction capability and voltage scaling. More specifically, the presented EP method requires no modifications to the processor pipeline and mitigates the generation of false-positive errors, ensuring stable operation of the system at high-efficiency points. The effectiveness of this strategy is demonstrated through its implementation in a near-threshold 32-bit microprocessor system with a modest 5.82% area overhead. Silicon measurements validate the adaptive EP system from 0.59 to 0.66 V (4–32 MHz) and confirm its removal of all voltage margins. Here, the EP technique reduces the energy consumption by 18.6–25.1% with respect to the signoff margins and it allows the system to operate without energy overhead compared to its ideal non-margined critical operation point, with less than a 5% throughput loss. [ABSTRACT FROM AUTHOR]

Benchmarks play an essential role in the performance evaluation of novel research concepts. Their effectiveness diminishes if they fail to exploit the available hardware of the evaluated microprocessor or, more broadly, if they are not consistent in comparing various systems. An empirical analysis of the consecrated Splash-2 benchmarks suite vs. the latest version Splash-4 was performed. It was shown that on a 64-core configuration, half of the simulated benchmarks reach temperatures well beyond the critical threshold of 105 °C, emphasizing the necessity of a multi-objective evaluation from at least the following perspectives: energy consumption, performance, chip temperature, and integration area. During the analysis, it was observed that the cores spend a large amount of time in the idle state, around 45% on average in some configurations. This can be exploited by implementing a predictive dynamic voltage and frequency scaling (DVFS) technique called the Simple Core State Predictor (SCSP) to enhance the Intel Nehalem architecture and to simulate it using Sniper. The aim was to decrease the overall energy consumption by reducing power consumption at core level while maintaining the same performance. More than that, the SCSP technique, which operates with core-level abstract information, was applied in parallel with a Value Predictor (VP) or a Dynamic Instruction Reuse (DIR) technique, which rely on instruction-level information. Using the SCSP alone, a 9.95% reduction in power consumption and an energy reduction of 10.54% were achieved, maintaining the performance. By combining the SCSP with the VP technique, a performance increase of 8.87% was obtained while reducing power and energy consumption by 3.13% and 8.48%, respectively. [ABSTRACT FROM AUTHOR]

Over the years, significant work has been done on high-integrity systems, such as those found in cars, satellites and aircrafts, to minimize the risk that a logic fault causes a system failure, thus having functional safety as a key requirement. In this study, we employ an innovative approach to harness the benefits of both Dual Modular Redundancy and Triple Modular Redundancy techniques within an Interleaved-Multi-Threading microprocessor core, by means of a microarchitecture design capable of dynamically switching from Dual Modular Redundancy to Triple Modular Redundancy in case of faults. We explain the quantitative results obtained from an extensive fault injection simulation campaign on the fault tolerant core compared with its previous version regarding fault tolerant capabilities. The results show that in several application cases the fault resilience improvement and the hardware and timing overhead are better compared to the lockstep-based dual core approach. The proposed technique achieves 98,6% fault mitigation at the expense of only 4 clock cycles for roll-back overhead, with no checkpointing redundancy.

Introduction: For individuals with limb loss, bone-anchored implants create a direct structural and functional connection to a terminal prosthesis. Here, we characterized the mechanical loads distal to the abutment during several functional performance tests in Service members with transfemoral (TF) limb loss, to expand on prior work evaluating more steady-state ambulation on level ground or slopes/stairs. Methods: Two males with unilateral TF limb loss and two males with bilateral TF limb loss participated after two-stage osseointegration (24 and 12 months, respectively). Tri-directional forces and moments were wirelessly recorded through a sensor, fit distal to the abutment, during six functional tests: Timed Up and Go (TUG), Four Square Step Test (FSST), Six Minute Walk Test (6MWT), Edgren Side-Step Test (SST), T-Test (TTEST), and Illinois Agility Test (IAT). Additionally, participants performed a straight-line gait evaluation on a 15 m level walkway at a self-selected speed (0.93-1.24 m/s). Peak values for each component of force and moment were extracted from all six functional tests; percent differences compared each peak with respect to the corresponding mean peak in straight-line walking. Results: Peak mechanical loads were largest during non-steady state components of the functional tests (e.g., side-stepping during SST or TTEST, standing up from the ground during IAT). Relative to walking, peak forces during functional tests were larger by up to 143% (anterior-posterior), 181% (medial-lateral), and 110% (axial); peak moments were larger by up to 108% (flexion-extension), 50% (ab/adduction), and 211% (internal/external rotation). Conclusions: A more comprehensive understanding of the mechanical loads applied to bone-anchored implants during a variety of activities is critical to maximize implant survivability and long-term outcomes, particularly for Service members who are generally young at time of injury and return to active lifestyles. [ABSTRACT FROM AUTHOR]

Modern electronic devices are supported by multicore processors and they have become an unavoidable part of recent technologies. The Arithmetic Logic Unit (ALU) is one of the indispensable parts of the Central Processing Unit (CPU) which performs most of the operations. Operations like multiplications, and exponentials consume more power than other normal operations. Power management is one of the major challenges in designing processors. To maximize speed and reduce power consumption, a new technique in Multiplier and ALU incorporated with a multicore processor has been proposed. The Proposed Approximate Compatible ALU (ACALU) is designed to perform specified operations that consume more power, using an advanced multiplication technique called the First One First Operand (FOFO) method. The selection process of eight bits is done by the FOFO method followed by error detection and error approximation is performed to get the accurate output. The ACALU performs these operations in the Approximate Computing Mode which utilizes only eight bits for the operations, thus reducing the power consumption. The results of several analyses between multipliers, ALUs, and microprocessors are provided. As we optimize the multiplier and ALU unit, the multicore processor is also enhanced. The proposed multicore processor is compared with the AMD processor and the latest INTEL processor and the comparison results show that the proposed technique is 95.2% and 97.8% more efficient than the existing processors. Thus, the power consumption is minimized and the performance speed is increased in the proposed multicore processor. [ABSTRACT FROM AUTHOR]

In this paper, an intelligent insole that contains five wide-range flexible capacitive pressure sensors is developed. The output signal of these five sensors is collected and processed by a portable microprocessor system, which is then transmitted to a cloud platform via a Wi-Fi module. The ensuing data visualization is constructed with a WeChat mini-program. The wide-range flexibility is achieved by employing composition materials with a high pressure-sensitive effect. A novel approach is proposed to fabricate flexible pressure-sensitive dielectrics, thereby significantly enhancing the sensitivity and detection range of pressure sensors. The fabrication process involves utilizing polydimethylsiloxane (PDMS) as a flexible substrate, incorporating nano-iron powder and polyvinylidene fluoride as sensitizing materials, and applying an external magnetic field to control the distribution of iron nanoparticles during the curing process of PDMS. Furthermore, a motion detection system tailored for these flexible sensors is developed. By integrating sensor networks with Internet of things technology, the application potential of wide-range flexible pressure sensors in kinematics and medical rehabilitation fields can be effectively realized. [ABSTRACT FROM AUTHOR]

Multiplication is a fundamental arithmetic operation in electronic processing units such as microprocessors and digital signal processors as it plays an important role in various computational tasks and applications. There exist many designs of synchronous multipliers in the literature. However, in the domain of Input–Output Mode (IOM) asynchronous design, there is relatively less published research on multipliers. Some existing works have considered quasi-delay-insensitive (QDI) asynchronous implementations of multipliers. However, the QDI asynchronous design paradigm, in general, is not area- and speed-efficient. This article presents an efficient alternative implementation of IOM asynchronous multipliers based on the concept of monotonic Boolean networks. The array multiplier architecture has been considered for demonstrating the usefulness of our proposition. The building blocks of the multiplier, such as the partial product generator, half adder, and full adder, were implemented monotonically. The popular dual-rail encoding scheme was considered for encoding the multiplier inputs and outputs, and four-phase return-to-zero handshaking (RZH) and return-to-one handshaking (ROH) were separately considered for communication. Compared to the best of the existing QDI asynchronous array multipliers, the proposed monotonic asynchronous array multiplier achieves the following reductions in design metrics: (i) a 40.1% (44.3%) reduction in cycle time (which is the asynchronous equivalent of synchronous clock timing), a 37.7% (37.7%) reduction in area, and a 4% (4.5%) reduction in power for 4 × 4 multiplication corresponding to RZH (ROH), and (ii) a 58.1% (60.2%) reduction in cycle time, a 45.2% (45.2%) reduction in area, and a 10.3% (11%) reduction in power for 8 × 8 multiplication corresponding to RZH (ROH). The multipliers were implemented using a 28 nm CMOS process technology. [ABSTRACT FROM AUTHOR]

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This research includes the study of the gait cycle for transfemoral amputation, which includes the kinetics and kinematics of the knee during different types of gaits, three different types of prosthetic knees are evaluated. The new model is designed to transform the hydraulic model into a smart, computerized limb with a microprocessor control unit that provides a high rotational speed to facilitate the process of turning and walking for lower limb amputees. The artificial knee mechanism was equipped with a Maxon EC motor, a socket, and a foot to form an integrated lower limb. This paper evaluates the proposed knee joint through a study of the gait cycle of the proposed joint and compares the results with those of other commercial joints to determine the closeness of the gait cycle results. [ABSTRACT FROM AUTHOR]

The HCS12 microcontroller and DRAGON12-Light Trainer boards are extensively utilized in microprocessor system design education. This paper details the rationale, approach, and outcomes from implementing the DRAGON12-Light Trainer board in teaching an upper-level undergraduate microprocessors course at Oakland University. The course's primary goal is for students to acquire the skills necessary to design both hardware and software for microprocessor-based systems, with applications across various industries. The paper assesses the effectiveness of employing the Motorola HCS12 microcontroller for its real-world relevance and integrates the Freescale CodeWarrior IDE v5.1 environment for software development. This research uniquely contributes by measuring the improvement in students' practical skills, specifically in hardware and software design using assembly and C programming, through hands-on lab assignments. It reports on the development of students' abilities to engage in microprocessor-based system design and critically evaluates the applied aspects of pedagogy by incorporating the DRAGON12-Light Trainer in lab exercises, such as those involving 'Measuring Human Reaction Time' and 'Servo motor interfacing.' Quantitative results, derived from student surveys and assessments, indicate significant improvements in students' programming competencies. The paper provides statistical results showcasing the increase in students' self-rated confidence levels in assembly and C language programming before and after course completion. Additionally, qualitative insights are discussed, reflecting students' experiences and the perceived applicability of the skills they acquired. These results underscore the pedagogical value of integrating practical training devices like the DRAGON12-Light Trainer board into microprocessors curricula. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) is introduced in systems with electrical machines, such as in electric drive systems, wind energy generating systems, and small and special machines, to remote monitor and control the operation for data acquisition and analysis. These systems can integrate with the equipment and retrofit the existing installations. At the end of the control loops there are always motors, or actuators, of big or small ratings, of rotating or linear movements, electrical or nonelectrical, which must produce the motion. This article analyses selected aspects of research and applications of IoT-based control in electric drive systems and of wind energy conversion systems with induction machines. Various applications and study cases of control systems of electrical machines with IoT technology are described. With the IoT-based control of induction machine systems operators can remotely monitor parameters and obtain accurate real-time feedback during fast changing duty cycle operation. Thus, IoT creates multipurpose instruments in the remote control of induction machines. The paper offers a comprehensive analysis of IoT-based control applications in the field of induction machines, with technical details of design, construction, experimental testing, and prototyping, that are useful to energy engineering specialists in the sector of electric drives and wind energy conversion systems. [ABSTRACT FROM AUTHOR]

With the advent of 6G Narrowband IoT (NB-IoT) technology, IoT security faces inevitable challenges due to the application requirements of Massive Machine-Type Communications (mMTCs). In response, a 6G base station (gNB) and User Equipment (UE) necessitate increased capacities to handle a larger number of connections while maintaining reasonable performance during operations. To address this developmental trend and overcome associated technological hurdles, this paper proposes a hardware-accelerated and software co-designed mechanism to support streaming data transmissions and secure zero-trust inter-endpoint communications. The proposed implementations aim to offload processing efforts from micro-processors and enhance global system operation performance by hardware and software co-design in endpoint communications. Experimental results demonstrate that the proposed secure mechanism based on the use of non-repeating keys and implemented in FPGA, can save 85.61%, 99.71%, and 95.68% of the micro-processor's processing time in key block generations, non-repeating checks, and data block transfers, respectively. [ABSTRACT FROM AUTHOR]

The digital balancing of the Furuta pendulum is studied when the time delay related to the digital control and the dynamics of the actuator have essential effects on stability. Such cases occur when the sampling rate of the digital control is low, that is, the control cycles are slow due to complex signal processing strategies and/or the implementation of cheap low-capacity microprocessors. A corresponding difficulty is that no direct velocity measurement is available. Critical sampling times are identified and stability charts are constructed and validated by experiments including the possible existence of quasi-periodic self-excited oscillations. [ABSTRACT FROM AUTHOR]

Quantum computing has grown extensively, especially in system design and development, and the current research focus has gradually evolved from validating quantum advantage to practical applications. In particular, nondeterministic‐polynomial‐time (NP)‐complete problems are central in numerous important application areas. Still, in practice, it is difficult to solved efficiently with conventional computers, limited by the exponential jump in hardness. Here, a quantum photonic microprocessor based on Gaussian boson sampling (GBS) that offers dynamic programmability to solve various graph‐related NP‐complete problems is demonstrated. The system with optical, electrical, and thermal packaging implements a GBS with 16 modes of single‐mode squeezed vacuum states, a universal programmable 16‐mode interferometer, and a single photon readout on all outputs with high accuracy, generality, and controllability. The developed system is applied to demonstrate applications in solving NP‐complete problems, manifesting the ability of photonic quantum computing to realize practical applications for conventionally intractable computations. The GBS‐based quantum photonic microprocessor is applied to solve task assignment, Boolean satisfiability, graph clique, max cut, and vertex cover. These demonstrations suggest an excellent benchmarking platform, paving the way toward large‐scale combinatorial optimization. [ABSTRACT FROM AUTHOR]

Copyright of Environmental & Social Management Journal / Revista de Gestão Social e Ambiental is the property of Environmental & Social Management Journal and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Teaching computer architecture (Comp-Arch) courses in undergraduate curricula is becoming more of a challenge as most students prefer software-oriented courses. In some computer science/engineering departments, Comp-Arch courses are offered without the lab component due to resource constraints and differing pedagogical priorities. This article demonstrates how students working in teams are motivated to study the Comp-Arch course and how instructors can increase student motivation and knowledge by taking advantage of hands-on practices. The teams are asked to design and implement a 16-bit MIPS-like processor with constraints as a specific instruction set, and limited data and instruction memory. Student projects include following three phases, namely, design, desktop simulator implementation, and verification using hardware description language (HDL). In the design phase, teams develop their Comp-Arch to implement specified instructions. A range of designs resulted, e.g., (a) a processor with extensive user-defined instructions resulting in longer cycle times (b) a processor with a minimal instruction set but with a faster clock cycle time. Next, teams developed a desktop simulator in any programming language to execute instructions on the architecture. Finally, students engage in Verilog Hardware Description Language (HDL) projects to simulate and verify the data-path designed during the initial phase. Student feedback and their current understanding of the project were collected through a questionnaire featuring varying Likert scale questions, some with a ten-point scale, and others with a five-point scale. Results of the survey show that the hands-on approach increases students' motivation and knowledge in the Comp-Arch course, which is centered around computer system design principles. This approach can also be effectively extended to related courses, such as Microprocessor Design, which delves into the intricacies of creating and implementing microprocessors or central processing units (CPUs) at the hardware level. Furthermore, the present study demonstrates that interactions, specifically through peer reviews and public presentations, between students in each phase increases their knowledge and perspective on designing custom processors. [ABSTRACT FROM AUTHOR]