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In this paper, the power gain, power-added efficiency (PAE) and linearity of power SiGe heterojunction-bipolar transistors at various temperatures have been presented. The power characteristics were measured using a two-tone load-pull system. For transistors biased with fixed base voltage, the small-signal power gain and PAE of the devices increase with increasing temperature at low base voltages, while they decrease at high base voltages. Besides, the linearity is improved at high temperature for all voltage biases. However, for devices with fixed collector current, the small-signal power gain, PAE, and linearity are nearly unchanged with temperature. The temperature dependence of power and linearity characteristics can be understood by analyzing the cutoff frequency, the collector current, Kirk effect and nonlinearities of transconductance at different temperatures. [ABSTRACT FROM AUTHOR]

Hot-carrier (HC) effects on high-frequency and RF power characteristics of Si/SiGe HBTs are investigated in this paper. By using the two-tone load-pull measurement, we find that not only the cutoff frequency, but also the output power performances of Si/SiGe HBTs are suffered by the HC stress. In this work, S-parameters and intrinsic elements of an equivalent hybrid-π model were used to validate the HC effects on high-frequency characteristics. With different bias conditions, the degradations of cutoff frequency, power gain, and linearity are found to be worse under constant base-current measurement than that under constant collector-current measurement. The HC-induced degradations on the current gain, transconductance, and ideality-factor of base and collector currents are analyzed to explain the experimental observations. [ABSTRACT FROM PUBLISHER]

We have investigated the radio frequency (RF) extrinsic resistance extraction for partially-depleted (PD) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs). Although the thick buried oxide in SOI devices can block the substrate coupling, the SOI neutral-body coupling effect is significant for RF applications. An equivalent circuit considering this effect has been proposed. Based on this equivalent circuit, a new model capturing the frequency dependence of extrinsic resistances has been derived. After considering the impact of quasi-neutral body, we have developed a physically accurate RF extrinsic resistance extraction methodology for PD SOI MOSFETs [ABSTRACT FROM PUBLISHER]

This letter reports the effect of using a p-minus substrate guard ring (psub GR) structure to reduce substrate noise coupling. A corresponding equivalent lump circuit model that predicts the substrate noise isolation behavior of this structure versus distance is also presented. For this particular study, it was found that integrating the psub GR into conventional GR designs can improve substrate noise isolation capabilities of conventional p+ guard rings and n-well guard rings by -15 dB and -5 dB, respectively. This scheme requires no extra masks or processes, and no special substrate material. [ABSTRACT FROM AUTHOR]