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Due to the availability of a large number of image editing software, it is very easy to find duplicate copies of original images. In such a situation, there is a need to develop a robust technique that can be used for the identification of duplicate copies apart from differentiating it from different images. In this paper, we have proposed an image hashing technique based on uniform Local Binary Pattern (LBP). Here, the input image is initially pre-processed before calculating the Local Binary Pattern (LBP) which is used for image identification. Experiments show that proposed hashing gives excellent performance against the Histogram equalization attack. The Receiver Operating Curve (ROC) indicates that the proposed hashing also performs better in terms of robustness and discrimination. Support Vector Machine (SVM) classifier shows that generated features can easily classify images into a set of similar and different images, and can classify new data with a high level of accuracy.

A novel inductance simulation circuit employing only two dual‐output voltage‐differencing buffered amplifiers (DO‐VDBAs) and a single capacitance (grounded) is proposed in this paper. The reported configuration is a purely resistor‐less realization that provides electronically controllable realized inductance through biasing quantities of DO‐VDBAs and does not rely on any constraints related to matched values of parameters. This structure exhibits excellent behavior under the influence of tracking errors in DO‐VDBAs and does not exhibit instability at high frequencies. The simple and compact metal‐oxide semiconductor (MOS) implementation of the DO‐VDBAs (eight MOS per DO‐VDBA) and adoption of grounded capacitance make the proposed circuit suitable for on‐chip realization from the perspective of chip area consumption. The function of the pure grounded inductance is validated through high pass/bandpass filtering applications. To test the proposed design, simulations were performed in the PSPICE environment. Experimental validation was also conducted using the integrated circuit CA3080 and operational amplifier LF‐356. [ABSTRACT FROM AUTHOR]

This paper aims to propose a new all-optical implementation of Fredkin gate using micro-ring resonator (MRR) based logical switches. The proposed all-optical Fredkin gate scheme employs only five MRRs connected in a parallel branch topology, therefore found very compact and ultrafast as compared to many previously reported designs. The presented gate enjoys all-optical operation with no requirement for an additional wavelength converter. A detailed discussion of the alloptical switching mechanism of MRR has been presented and the logical behavior of the presented Fredkin gate has been demonstrated by using MATLAB simulations. [ABSTRACT FROM AUTHOR]

Images are considered to be natural carriers of information, and a large number of images are created, exchanged and are made available online. Apart from creating new images, the availability of number of duplicate copies of images is a critical problem. Hashing based image copy detection techniques are a promising alternative to address this problem. In this approach, a hash is constructed by using a set of unique features extracted from the image for identification. This article provides a comprehensive review of the state-of-the-art image hashing techniques. The reviewed techniques are categorized by the mechanism used and compared across a set of functional & performance parameters. The article finally highlights the current issues faced by such systems and possible future directions to motivate further research work.

The presence of turning points (stationary points like maxima and minima) in the Parameter-versus-state map (PSM) curve of a memristor can be beneficial in several memristive uses like multi-level logic design, multi-bit memories, and chaos generation circuits. Surprisingly the memristors with these types of PSM curves exhibit multiple crossing points in the transient input v-i contours. In this paper, the memductance model has been derived for such non-linear memristors exhibiting multi-cross-over characteristics. In the presented framework, the coefficients-related condition for the multi-turning point PSM curve has been derived, a necessary condition for the multi-crossing v-i contour. The condition related to the memristor operating parameters has also been reported taking both input signal and initial states into consideration. To realise the derived memductance model corresponding to the three cross-over memristive behaviour, an OTA-based memristor emulator has been developed. Unlike some existing fractional order non-symmetric multi-crossing memristor emulators, the proposed emulator circuit realises an integer order memristor function operating at moderate frequencies. The realised emulator uses only four OTAs and three grounded passive circuit elements with no external multiplier. For the CMOS implementation of employed OTA, the simulation results are obtained to verify the three pinch-off behaviour. [ABSTRACT FROM AUTHOR]

To polish the surface of silicon wafers, the impact of ultrasonic vibration assistance on the double disc chemo-magnetorheological finishing was investigated. The in-house setup was fabricated to provide vibrations to the workpiece during the polishing in the longitudinal direction. The central composite design (CCD) approach was adopted in experiment planning to understand the influence of process parameters (like magnets rotation, abrasive concentration, and ultrasonic power) on the surface roughness (% Δ R a ). A 3D optical profilometer was employed to check the surface roughness of the polished wafers. The individual and interaction of significant process factors affecting were determined using the analysis of variance (ANOVA) technique. A regression equation based on response surface methodology was developed. The process parameters were optimized using a genetic algorithm to maximize the change in surface roughness before and after polishing. The experiment performed at an optimized set resulted in an average surface finish of 3.4 nm. A 3D surface plots and scanning electron microscopy (SEM) were used to understand the changes on the surfaces of unpolished and polished samples at the optimized parameters. [ABSTRACT FROM AUTHOR]

The purpose of this research paper is to present a new all-optical scheme to implement the logical behavior of generalized n th-order (2 n :1) multiplexer logic. The proposed all-optical design is based on micro-ring resonator (MRR)-based all-optical switches and constructed by using "2 n + 1 -2" MRR structures, arranged in a series " n " stage architecture. The presented configuration enjoys advantageous features like compact-sized systematic structure and ultra-fast speed. To validate the logical behavior of the proposed n th-order multiplexer, a second-order (22:1) multiplexer is derived (from the proposed scheme) and discussed. Further, the usability of the presented all-optical multiplexer is demonstrated by developing an all-optical reconfigurable logic gate that can be reconfigured to perform various logic operations. To verify the logical behavior of MRR-based all-optical switch and presented all-optical multiplexer logic, numerical simulations through MATLAB software have been performed. The reported reconfigurable logic structure is also simulated in the MATLAB environment to validate the desired behavior. [ABSTRACT FROM AUTHOR]

A compact memristor emulator structure using ten CMOS transistors-based structures is presented with a fully floating circuit configuration. Along with the use of such a compact CMOS structure to form a transconductance cell, the circuit requires only a single grounded capacitance and two external MOS transistors. Unlike several externally employed transconductance cells-based memristor emulators reported previously, the proposed circuit can be considered a compact architecture due to the non-employment of any external multiplier and floating passive elements, and also a lesser number of used transistors. The electronic tunability and wide-band operating frequency range (400 Hz–50 MHz) are the other attractive features of the proposed emulator. The circuit has been tested by performing simulations using PSPICE with 0.18 μ m CMOS technology. The presented simulation results clearly show the ideal non-volatile nature found in the realized memristor, which has also been employed in a neuron circuit based on the proposed emulator depicted in the article. The neuron circuit has been used to generate a spike output by applying a post-synaptic signal equivalent DC input. Finally, the circuit idea of the proposed memristor emulator has been tested by using commercial IC LM13700. [ABSTRACT FROM AUTHOR]

The article explores the compact emulation of the inverse memristor through a circuit-based approach. It introduces a floating emulator architecture that incorporates a dual output OTA (Operation Transconductance Amplifier) and DVCC (Differential Voltage Current Conveyor), along with two grounded passive elements, to achieve the emulation of an inverse memristor. The utilization of grounded resistance allows for tunability over the realized behaviour. A key contribution of this research is the novel application of the inverse memristor to extend the operating frequency range of any memristor emulator circuit. Validation of the proposed emulator circuit, in both incremental and decremental modes, along with its application, is conducted using PSPICE-generated simulation results in the 0.18 µm TSMC CMOS technology. Additionally, an inverse memristor emulator configuration employing the IC LM13700 is presented, and its functionality is tested through a breadboard implementation. [ABSTRACT FROM AUTHOR]