Search

The emergence of four-level pulse amplitude modulation (PAM-4) standards to increase data rates motivates the use of receiver front ends that utilize high-speed analog-to-digital converters (ADCs) followed by digital signal processing (DSP) to provide robust digital equalization. This paper presents an ADC-based PAM-4 receiver employing a 32-way time-interleaved, 2-bit/stage, 6-bit successive approximation register (SAR) ADC with a single capacitive reference digital-to-analog converter (DAC) and a digital equalizer consisting of a 12-tap feed-forward equalizer (FFE) and a two-tap decision-feedback equalizer (DFE). A new digital DFE architecture that reduces the complexity of a PAM-4 DFE to that of a binary non-return-to-zero (NRZ) DFE, while simultaneously nearly doubling the maximum achievable data rate, is presented. Partial analog equalization is provided in the receiver front end in the form of a programmable two-stage continuous-time linear equalizer (CTLE) and a three-tap FFE that is embedded in the ADC using a non-binary FFE DAC to improve the FFE coefficient coverage space. This partial analog equalization allows placement of the digital baud-rate clock and data recovery (CDR) system’s Mueller–Muller phase detector directly at the ADC output to avoid excessive loop delay. Fabricated in GP 65-nm CMOS, the receiver achieves 32-Gb/s operation at a bit error rate (BER) $10^{-9}$ with a 30-dB loss channel and 52-Gb/s operation at a BER $10^{-6}$ with a 31-dB loss channel without utilizing any transmit equalization. The complete ADC-based receiver achieves a 52-Gb/s power efficiency of 8.06 pJ/bit, including all the front end, ADC, and DSP power.

Serial link receivers with high-speed analog-to-digital converters (ADCs) can utilize powerful digital-domain equalizers and support multilevel modulation schemes. This paper presents a hybrid statistical modeling framework for ADC-based serial link receivers. The framework builds upon the existing statistical modeling techniques for mixed-signal receivers and adds the support of ADC quantization noise, radix errors [integral nonlinearity and differential nonlinearity (INL/DNL)], and time-interleaving mismatches. A rapid purely statistical simulation mode is utilized to model systems with small front-end nonlinearity and ADC INL/DNL. To include ADC INL/DNL, a hybrid approach is presented with an initial short transient simulation. The presented modeling framework is used to explore the effectiveness of embedding an analog feed-forward equalizer (FFE) in the ADC of a 10-Gb/s receiver. Measurement results of a 10-Gb/s ADC-based receiver prototype with a three-tap embedded FFE in the ADC and a digital four-tap FFE and three-tap decision feedback equalizer are presented to validate the presented framework.

While high-speed analog-to-digital converter (ADC) front-ends in serial link receivers enable flexible and powerful digital signal processing-based (DSP-based) equalization, the robustness and power consumption of these ADCs can limit overall receiver energy efficiency. This paper presents a 25 GS/s 6b 8-way time-interleaved multi-bit search ADC that employs a soft-decision selection algorithm to relax track-and-hold (T/H) settling requirements and improve ADC metastability tolerance. T/H bandwidth is also improved with a new shared-input double-tail three-latch structure. Fabricated in general purpose 65 nm CMOS, the ADC occupies 0.24 mm2 total area. A signal-to-noise and distortion ratio (SNDR) of 29.6 dB is achieved at Nyquist while consuming 88 mW from a 1 V supply, translating into a figure-of-merit of 143 fJ/conversion step. A measured $^{-10}$ metastability error rate demonstrates the effectiveness of the soft-decision selection algorithm.

CMOS ADC-based serial link receivers enable powerful digital equalization and symbol detection techniques for high data rate operation over electrical and optical wireline channels. Common ADC architectures and equalization techniques that allow 10 Gb/s and higher operation are surveyed in this article. As time-interleaving is most often employed to achieve these high sampling rates, the associated errors and calibration techniques are presented. The impact of ADC quantization noise on receiver performance and how this can be improved via embedded partial analog equalization are detailed. A description of a 65 nm CMOS hybrid ADC-based receiver architecture that employs a 3-tap analog FFE embedded inside a 6-bit asynchronous successive approximation register (SAR) ADC and a per-symbol dynamically enabled digital equalizer operating at 10 Gb/s concludes the discussion.

While analog-to-digital converter (ADC)-based serial link receivers enable powerful digital equalization for high data rate operation, the ADC and digital equalization power consumption is a key concern in applications that support operation over a wide range of channels with varying amounts of intersymbol interference (ISI). This paper presents a hybrid ADC-based receiver architecture which employs a 3-tap analog feed-forward equalizer (FFE) embedded inside a 6 bit asynchronous successive approximation register (SAR) ADC and a per-symbol dynamically enabled digital equalizer, resulting in both reduced equalizer complexity and power consumption. Fabricated in general purpose (GP) 65 nm CMOS, the hybrid ADC-based receiver occupies $0. 81\; \text{mm}^{2}$ area. 10 Gb/s operation is verified for FR4 channels with up to 36.4 dB attenuation, with the proposed dynamic enabling of the digital 4-tap FFE and 3-tap decision feedback equalizer (DFE) on a per-symbol basis resulting in nearly 30 mW savings and an overall receiver power less than 90 mW.

This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA drivers and segments are switched on and off according to signal power; thus, the PA power consumption correlates with the power of the input signal. Binary power gain variations due to PA segmentation are dynamically compensated in the digital domain. The proposed solution overcomes the tradeoffs between power efficiency and linearity by employing the digital predistortion technique. The PA is implemented in a 40 nm CMOS process. It delivers a saturated output power of 35 dBm with 44.9% peak power-added efficiency (PAE) and a linear gain of 38 dB. The adjacent channel leakage ratio (ACLR) at $\pm {5}\;\text{MHz}$ at a maximum linear output power of 31 dBm for a baseband WCDMA signal is $- {35}.{8}\;\text{dBc}$ .

A reference switching pre-emphasis (RSP) technique is proposed for successive approximation register (SAR) ADC in order to improve the SAR DAC settling time, which limits the conversion speed of conventional SAR ADCs. While SAR ADCs that employ redundancy techniques relax DAC settling requirements by overlapping search spaces, this requires more conversion steps which offsets the benefit from the DAC settling relaxation, especially for low–medium resolution SAR ADCs. The proposed RSP technique improves DAC settling by breaking its dependence on ADC resolution and achieves up to 71% speedup of DAC settling relative to a conventional DAC switching scheme without introducing additional conversion steps or significant hardware overhead.

A process-variation resilient current mode logic (CML) is presented. The proposed CML employs time-reference-based adaptive biasing chain with replica load to address performance degradation over the process variations. It adjusts variable load resistor to simultaneously regulate time constant, voltage swing, level shifting, and DC gain. The prototype demonstrates the process-variation resiliency of the proposed solution by showing performance degradation over the process corners. Over 20% of polygate resistance variation, the proposed CML suppresses the degradation of speed and rms jitter less than 4.3% and 0.15 ps while conventional CML results in 13% and 3.8-ps degradation, respectively.

State-of-the-art portable ultrasound imaging systems employ a small transducer array and a low carrier frequency to fit stringent constraints on power and form factor, and this tends to compromise the ultrasound imaging quality. In this paper, we present a low-complexity low-power asynchronous compressed beamformer (ACB) for portable diagnostic ultrasound. The proposed ACB integrates asynchronous sampling and compressive sensing (CS), and is capable of reducing data conversion power and handling a large data volume at the mixed-signal interface. A high-rate continuous-time ternary encoding (CT-TE) scheme eliminates the need for interpolation filters and coordinate rotation digital computer (CORDIC) units typically used in a conventional architecture. A split-projection least squares (SPLS) signal reconstruction algorithm is applied that replaces high-cost nonlinear signal recovery with a series of low-complexity and independent linear problems. Experiments with measured ultrasound data demonstrate the proposed ACB architecture, and the SPLS reconstruction algorithm achieves 9-fold data compression compared with Nyquist sampling.

High-speed ADC front-ends in wireline receivers allow for implementing flexible, complex, and robust equalization in the digital domain, as well as easily supporting bandwidth-efficient modulation schemes, such as PAM4 and duobinary. However, the power consumption of these ADC front-ends and subsequent digital signal processing is a major issue. This paper presents a 64-way 6 bit 10 GS/s time-interleaved successive-approximation-based ADC front-end that efficiently incorporates a two-tap embedded FFE and a one-tap embedded DFE, providing the potential for a lower complexity back-end DSP and/or decreased ADC resolution. Fabricated in a 1.1V GP 65nm CMOS process, the ADC with embedded equalization achieves 0.48 pJ/conv.-step FOM, while consuming 79.1mW and occupying 0.33 mm 2 core ADC area. The effectiveness of the embedded FFE and DFE is demonstrated with significant timing margin improvement observed for 10 Gb/s operation over several FR4 channels.

ADC-BASED serial link receivers are emerging in order to scale data rates over high attenuation channels. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-efficient receiver. This paper presents a 6-b 1.6-GS/s ADC with a novel embedded DFE structure. A redundant cycle technique is proposed for a time-interleaved SAR ADC, which relaxes the DFE feedback critical path delay with low power/area overhead. The 6-b prototype ADC with embedded one-tap DFE is fabricated in an LP 90-nm CMOS process and achieves 4.75-bits peak ENOB and 0.46 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. Enabling the embedded DFE while operating at 1.6 Gb/s over a 46-in FR4 channel with 14-dB loss at Nyquist bandwidth opens a previously closed eye and allows for a 0.2 UI timing margin at a BER=10-9. Total ADC power including front-end T/Hs and reference buffers is 20.1 mW, and the core time-interleaved ADC occupies 0.24 mm 2 area.

Compressive sensing (CS) holds new promises for the digitization of wideband frequency-domain sparse signals at sub-Nyquist rate sampling without compromising the reconstruction quality. In this paper, the impact of ADC nonlinearity in a CS receiver for frequency-domain sparse signals is investigated. In a mixed-signal CS system, signals are randomized before sampling. The signal spectrum at each building block in the mixed-signal CS system is analyzed and compared to a conventional Nyquist-rate sampling system. It is shown that the signal randomization in a mixed-signal CS system is able to spread the spurious energy due to ADC nonlinearity along the signal bandwidth, rather than the concentration of harmonic distortion on a few frequencies as it is the case for a conventional ADC. As a result, this paper shows that a significant ADC SFDR (Spurious Free Dynamic Range) improvement is achieved in a CS receiver when processing sparse signals. Simulation results are reported which are in good agreement with the qualitative analysis.

A wideband low-noise amplifier (LNA), which is a key block in the design of broadband receivers for multiband wireless communication standards, is presented in this paper. The LNA is a fully differential common-gate structure. It uses multiple feedback paths, which add degrees of freedom in the choice of the LNA transconductance to reduce the noise figure (NF) and increase the amplification. The proposed LNA avoids the use of bulky inductors that leads to area and cost saving. A prototype is implemented in IBM 90-nm CMOS technology. It covers the frequency range of 100 MHz to 1.77 GHz. The core consumes 2.8 mW from a 2-V supply occupying an area of 0.03 mm2. Measurements show a gain of 23 dB with a 3-dB bandwidth of 1.76 GHz. The minimum NF is 1.85 dB, while the average NF is 2 dB across the whole band. The LNA achieves a return loss greater than 10 dB across the entire band and a third-order input intercept point IIP3 of - 2.85 dBm at the maximum gain frequency.

Nonlinearities in transmitter circuits, such as power amplifiers, cause degradation in system performance and adjacent-channel spectral growth interference. Polyphase multipath is considered among the techniques that can compensate the nonlinearities, creating a clean output spectrum. However, the polyphase technique requires analog phase shifters that consume considerable power. Aiming at reducing the power consumption, this brief presents a novel multiphase multipath technique with digital phase shifters. The technique is capable of canceling most of the harmonic and intermodulation products produced by a current-output nonlinear circuit to achieve the required linearity. The proposed system has advantages over existing polyphase techniques in power consumption, accuracy, and flexibility. However, it lacks image rejection and local oscillator harmonic cancellation. Detailed analyses and simulations of the new technique are provided to show the effectiveness of the harmonic distortion cancellation.

A novel technique to reduce die area on a discrete-time sinc2↓2 filter for charge sampling is proposed. An SNR comparison of the conventional and the proposed topology reveals that the new technique saves 25% die area occupied by the sampling capacitors of the filter. The idea is also extended to implement higher downsampling factors, and greater percentage of area is saved as the downsampling factor is increased. The proposed filter also has the topological advantage over previously reported works of allowing the designers to use active integration to charge the capacitance, which is critical in obtaining high linearity.

Transform-domain (TD) receivers expand the received signal over a basis set, and then operate on the basis coefficients. An analog computation of the basis coefficients efficiently parallelizes the signal for digital processing, relaxing the sampling requirements and enabling parallel digital processing at a much lower rate. Frequency-domain (FD) sampling, as a special case of TD sampling, has been proposed to parallelize the sampling process in broad-band communication receivers. The flexibility and scalability of TD receivers allow for the design of receivers that can cope with a large range of narrow-band and broad-band communications standards. A theoretical TD receiver design example is provided which is capable of processing GSM, Bluetooth, IEEE802.11g, Wimax, and UWB in just one configurable front-end. An example of spectrum sensing in cognitive radio is also provided.

We consider a mixed-signal ultra wideband (UWB) direct-sequence spread-spectrum (DS-SS) receiver. The receiver expands the signal over a basis set, and then operates on the basis coefficients. An analog computation of the basis coefficients efficiently parallelizes the signal for digital processing, relaxing the sampling requirements and enabling parallel digital processing at a much lower rate. Bit error rate (BER) performance is evaluated, as well as distortion due to basis truncation. The parallel processing also facilitates efficient interference mitigation. Various models for interference including adjacent multicarrier interference are developed and analyzed. Several simulation results confirm the analysis and provide insight into quantization error, basis truncation distortion, and the impact of the UWB channel. We show that in the AWGN uncoded case for SNR < 10 dB, the receiver can be operated at almost half the Nyquist rate with only 1 dB of performance loss. Moreover, when a common convolutional code is employed, the aggregate sampling rate can be 37.5% lower than Nyquist rate with little loss in receiver performance.

This paper presents a mixed-signal frequency-domain implementation of the autocorrelation receiver used in the detection of ultra-wideband communication signals that are modulated with transmitted-reference signaling. The digital receiver architecture is based on samples provided by an analog-to-digital converter (ADC) in the frequency domain. Among the advantages of the new receiver are the relaxation of the conversion speed achieved by the inherent parallel architecture of the frequency-domain ADC and the flexibility and simplicity of an all-digital receiver architecture that follows the mixed-signal ADC radio front-end. The paper provides the symbol detection formulas and the corresponding system implementation and makes comparisons with the conventional time-domain implementations. Additionally, a time synchronization technique for the new receiver structure is proposed, which makes the receiver insensitive to any time offset at the pulse level. Furthermore, as a particular case of great practical interest, we consider a single bit for the ADC implementation, and we show with experimental results that the resultant frequency-domain mono-bit digital receiver provides a performance gain that increases with the number of frequency samples, when compared with its time-domain counterpart.

This paper introduces a multicarrier communication receiver for broadband applications based on analog to digital conversion (ADC) of the received signal in the frequency domain. The samples of the spectrum of the received signal are used in the digital receiver to estimate the transmitted symbols through a matched filter operation in the discrete frequency domain. The proposed receiver is aimed at the reception of high information rates in a multicarrier signal with very large bandwidth. Thus, the receiver architecture provides a solution to some of the challenging problems found in the implementation of conventional wideband multicarrier receivers based on time-domain ADC, since It efficiently parallelizes the A/D conversion reducing the sampling speed requirements. We show that the sampling rate requirements are relaxed as the number of frequency samples is increased, which introduces a trade-off between complexity and sampling rate. The new receiver possesses additional advantages, including scalability with increasing frequency samples, the possibility of optimally allocating the available number of bits for the ATD conversion across the frequency domain samples which potentially reduces the distortion introduced by the high-speed ADC, narrowband interference suppression that can be directly carried out in the frequency domain, and inherent robustness to frequency offset which makes it an attractive solution when compared with traditional multicarrier receivers. We also investigate how the proposed receiver responds to common multicarrier communication receiver problems such as phase noise and channel frequency selectivity.

We consider analog to digital (A/D) conversion, based on the quantization of coefficients obtained via the projection of a continuous time signal over a set of basis functions. The framework presented here for A/D conversion is motivated by the sampling of an input signal in domains which may lead to significantly less demanding A/D conversion characteristics, i.e., lower sampling rates and lower bit resolution requirements. We show that the proposed system efficiently parallelizes the analog to digital converter (ADC), which lowers the sampling rate requirements by increasing the number of basis functions on which the continuous time signal is projected, leading to a tradeoff between sampling rate reduction and system complexity. Additionally, the A/D conversion resolution requirements can be reduced by optimally assigning the available number of bits according to the variance distribution of the coefficients obtained from the signal projection over the new A/D conversion domain. In particular, we study A/D conversion in the frequency domain, where samples of the continuous signal spectrum are taken such that no time aliasing occurs in the discrete time version of the signal. We show that the frequency domain ADC overcomes some of the difficulties encountered in conventional time-domain methods for A/D conversion of signals with very large bandwidths, such as ultra-wideband (UWB) signals. The proposed A/D conversion method is compared with conventional ADCs based on pulse code modulation (PCM). Fundamental figures of merit in A/D conversion and system tradeoffs are discussed for the proposed ADC. The signal-to-noise and distortion ratios of the frequency domain ADC are presented, which quantify the impact of the most critical impairments of the proposed ADC technique. We also consider application to communications receivers, and provide a design example of a multi-carrier UWB receiver.

Ultrawideband systems employ short low-power pulses. Analog receiver designs can accommodate the required bandwidths, but they come at a cost of reduced flexibility. Digital approaches, on the other hand, provide flexibility in receiver signal processing but are limited by analog-to-digital converter (ADC) resolution and power consumption. In this paper, we consider reduced complexity digital receivers, in which the ADC is limited to a single bit per sample. We study three one-bit ADC schemes: 1) fixed reference; 2) stochastic reference; and 3) sigma-delta modulation (SDM). These are compared for two types of receivers based on: 1) matched filtering; and 2) transmitted reference. Bit-error rate (BER) expressions are developed for these systems and compared to full-resolution implementations with negligible quantization error. The analysis includes the impact of quantization noise, filtering, and oversampling. In particular, for an additive white Gaussian noise channel, we show that the SDM scheme with oversampling can achieve the BER performance of a full-resolution digital receiver.

This paper introduces the concept of complex weighted median (WM) filtering admitting complex weighting. Unlike previous approaches in the literature that only allowed positive real-valued weights, the new WM structures exhibit improved performance as they exploit the richness of unrestricted complex weighting. To this end, the newly defined complex WM structures synthesize filtering operations, whereas the prior structures could only attain smoothing properties due to the inherent constraints imposed on the weights. In order to overcome the two-dimensional (2-D) search burden associated with the computation of the complex WM, two fast, robust, and very efficient approximations are introduced. Adaptive optimization algorithms for their design are developed leading to simple LMS-type weight updates. Several simulations are shown illustrating the performance of the new complex WM filter structures.

This paper presents a data estimation scheme for wide band multichannel charge sampling filter bank receivers together with a complete system calibration algorithm based on the least mean squared (LMS) algorithm. A unified model has been defined for the receiver containing all first order mismatches, offsets, imperfections, and the LMS algorithm is employed to track these errors. The performance of this technique under noisy channel conditions has been verified. Moreover, a detailed complexity analysis of the calibration algorithm is provided which shows that sinc filter banks have much lower complexity than traditional continuous-time filter banks.

A simple feedforward spectral shaping technique for the pulsewidth jitter induced errors in digital-to-analogue converters (DACs) is presented. The proposed technique features a feedforward combination of the conventional rectangular-pulse switched-current DAC and a discrete-time switched-capacitor DAC to achieve spectral shaping for the jitter induced error. The benefit of this hybrid DAC solution using error specral shaping is illustrated in the context of feedback DACs used in continuous-time ΔΣ modulators. Simulation results show that the jitter tolerance of the proposed DAC solution is equivalent to that of the commonly used jitter-tolerant exponentially-decaying waveform switched-capacitor-resistor DAC structure, but at much more relaxed slew-rate requirement on the op-amp used in the DAC load circuit, which translates into significant power savings.

Stringent jitter specifications in the sampling clocks severely limit the evolution of future generations of wideband high-performance receivers. For instance, it is shown that a conventional single-channel receiver requires 1.5 ps of jitter standard deviation to achieve 34 dB signal-to-noise ratio (SNR) when sampling a 10 GHz orthogonal frequency division multiplexing (OFDM) signal. This study presents an analytical framework for the design of jitter-tolerant multi-channel filter-bank OFDM receivers. Additionally, the study presents an optimisation method for the filter-bank bandwidth that is able to reduce the filter-bank order saving power and area and achieving optimal signal quality. Simulations that confirm the analytical result show that 34 and 38 dB SNR are achieved with 5-channel and 10-channel receivers, respectively, when using second-order bandwidth-optimised filter-bank that samples a 10 GHz OFDM signal tolerating 6 ps of jitter.

The sensitivity of single-bit continuous-time (CT) ΔΣ analogue-to-digital converters to out-of-band (OOB) blockers received in companion with desired signals is investigated. In essence, the residual interferer signal appearing at the output of the CT loop filter can flip the single-bit quantiser decision near the zero crossings of the loop filter output signal. An intuitive analysis of this effect on the performance of single-bit ΔΣ modulators in the presence of OOB interferers is provided. System level simulations for a single-bit fifth-order CT ΔΣ modulator at an oversampling ratio of 40 have been carried out. A reduction in the achievable signal-to-noise-plus-distortion ratio, that can be as large as 10 dB when applying a 0 dBFS OOB blocker tone along with a weak -75 dBFS desired tone, has been observed. The simulation results show good agreement with the adopted theoretical discussion.

A CMOS single supply operational transconductance amplifier (OTA) is reported. It has high power supply rejection capabilities over the entire gain bandwidth. The OTA is fabricated using the AMI 0.5 m CMOS process. Measurements show power supply rejection ratio (PSRR) of 120 dB to 10 kHz. At 10 MHz, PSRR is 40 dB. The high performance PSRR is achieved using a high impedance current source and two noise reduction techniques. The OTA offers very low current consumption of 25 A from a 3.3 V supply. It is suitable for applications such as low drop out voltage regulators.

A technique to implement a discrete-time (DT) sinc3 ↓2 filter for windowed integration samplers is proposed. The topology reduces the idle time of the integration capacitors at the expense of a small complexity overhead in the clock generation, thereby saving 33% of the die area compared to the currently existing topology. Circuit level simulations in 45 nm CMOS technlogy shows good agreement with the predicted behaviour obtained from the analaysis.