1. A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience
- Author
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Rick Wong, Haibin Wang, Rui Liu, S. T. Shi, Yuanqing Li, Sanghyeon Baeg, L. Chen, Issam Nofal, A.-L. He, Mo Chen, Qiong Wu, Gang Guo, and S.-J. Wen
- Subjects
010302 applied physics ,Nuclear and High Energy Physics ,Engineering ,010308 nuclear & particles physics ,business.industry ,Transistor ,Hardware_PERFORMANCEANDRELIABILITY ,01 natural sciences ,law.invention ,Soft error ,Nuclear Energy and Engineering ,CMOS ,law ,0103 physical sciences ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,Redundancy (engineering) ,Electrical and Electronic Engineering ,business ,Flip-flop ,Hardware_LOGICDESIGN ,Electronic circuit - Abstract
A flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and manufactured in a 65-nm CMOS bulk technology. Experimental characterization results of their alpha and heavy ions soft-error rates verified the superior hardening performance of the proposed design over the other two circuits.
- Published
- 2017
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