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The Hamming code or Linear block code is used in communication to identify and repair errors. Redundancy bits are introduced to the Hamming communication network (HCN) for error detection and correction. It can detect two errors and correct one error. Quantum-dot Cellular Automata (QCA) is used for designing circuits with high switching speed and low energy dissipation. This work proposes a cost-effective QCA-based (7, 4) Hamming encoder and decoder design. Hamming encoder is designed using coplanar structure and the error detector used in Hamming decoder uses a multilayer structure. The effort is to optimize the area, cost, and energy dissipation. The work proposes a coplanar (7, 4) Hamming encoder and decoder. Hamming decoder is implemented in two parts a syndrome calculator and an error detector. Proposed (7, 4) Hamming encoder circuit reduces cell count by 49.47% compared to [1] and 9.52% compared to [12]. The proposed (7, 4) syndrome calculator has reduced cell count by 56.54%, an 11.11% reduction in total area compared to [1]. The proposed design reduces the cell area, QCA cost, and also energy dissipation. The designs are realized and QCA parameters are assessed in QCADesigner2.0.3 and energy is analyzed in QCADesigner-E. [ABSTRACT FROM AUTHOR]

Wireless communication is a fast-growing industry and recent developments focus on improving certain aspects of the area and reducing the power consumption while maintaining the frequency of operation. Phase Locked Loop (PLL) is an integral part of communication circuits which operate at very high frequencies. Phase Frequency Detector (PFD) is the first block of PLL and is key in determining the computational capacity of the PLL. The power consumption of the PFD has to be reduced to minimize the overall power consumption of PLL. The PFD architecture used is based on Double Edged Triggered D Flip-Flop (DET-DFF), which is free of dead zone. Stack, LECTOR, AVLS and hybrid low-power approaches are implemented to reduce the power consumption of DET-DFF based PFD architectures. The PFDs power, delay and power delay product analysis is performed using Cadence Virtuoso and Spectre in CMOS 180 nm and 90 nm technology. A power reduction of upto 32 % has been observed while keeping the transistor count to a minimum. [ABSTRACT FROM AUTHOR]

In any wide-range processing system, rapid interconnecting networks are employed between the processing modules and embedded systems. This study deals with the optimized design and implementation of Switching Element (SE) which operates in four modes, accepting two inputs and delivering two outputs. The Shuffle-Exchange Network (SEN) can be used as a single-stage as well as a multi-stage network. SEN is used as an interconnection architecture which is implemented with exclusive input-output paths with simple design. The SE acts as a building block to the Multi-stage Shuffle-Exchange Network (M-SEN) with facilities to perform unicast and multicast operation on the inputs. An 8 x 8 M-SEN model is also implemented, which works in three modes of communication, termed as "One-to-One", "One-to-Many" and "One-to-All" M-SEN configuration. All the QCA circuits have been implemented and simulated using CAD tool QCADesigner. The proposed QCA-based M-SEN design is better in terms of area occupied by 14:63 %, average energy dissipation by 22:75 % and cell count with a reduction of 84 cells when compared to reference M-SEN architecture. The optimization of the design in terms of cell count and area results in lesser energy dissipation and hence can be used in future-generation complex networks and communication systems. [ABSTRACT FROM AUTHOR]