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Undetectable faults result from logic redundancies and constraints on applicable tests. The presence of an undetected (undetectable or aborted) fault implies that a test, which would have covered its site, is missing from the test set. When undetected transition faults form a path, the missing tests imply that (small) delay defects along the path may not be detected even if they are detectable. The goal of this article is to provide additional coverage for paths of undetected transition faults by using two-cycle gate-exhaustive faults for subcircuits (gates) that wrap the paths. The use of gate-exhaustive faults alleviates the need to model delay defects along the paths, or use path delay faults that may also be undetectable. The article defines the target paths, and gates that wrap them, for which two-cycle gate-exhaustive faults can be defined. Experimental results for benchmark circuits demonstrate the discussion. [ABSTRACT FROM AUTHOR]

Logic diagnosis to support yield improvement requires the collection of fail data. The full fail data for a faulty unit consist of the tests and observable outputs where the faulty unit produces faulty values. The volume of fail data that needs to be collected can be excessive. A recent solution is to use only pass/fail data for as many tests as possible. With pass/fail data for a test, the full fail data is replaced with a single bit that indicates whether the faulty unit passed or failed the test. However, with conventional scan-based tests, some tests require the full fail data to preserve the diagnostic quality of the test set. This article observes that the use of scan-based tests under bounded transparent-scan increases the diagnostic quality achievable using only pass/fail data. The article describes a test generation procedure for bounded transparent scan that uses only pass/fail data, and targets the same diagnostic quality as a conventional scan-based test set with full fail data. The experimental results demonstrate that, for many of the benchmark circuits considered, a bounded transparent-scan test set with pass/fail data matches the diagnostic quality of a conventional scan-based test set with full fail data. [ABSTRACT FROM AUTHOR]

Scan-based tests were shown to create nonfunctional operation conditions that can cause a fault-free circuit to exhibit the appearance of a delay fault. Scan-based tests that are extracted from functional test sequences avoid nonfunctional operation conditions during their functional capture cycles and are referred to as functional scan-based tests. This brief observes that the stuck-at fault coverage of functional single-cycle tests is significantly higher than the transition fault coverage of functional launch-on-capture (LOC) tests that are extracted from the same sequences. To bridge the fault coverage gap, this brief describes a procedure that extracts both functional LOC and close-to-functional launch-on-shift (LOS) tests together from functional test sequences. The LOS tests have the unique property that their functional capture cycles consist of functional single-cycle tests. Experimental results for benchmark circuits show significant reductions in the fault coverage gap between stuck-at and transition faults. [ABSTRACT FROM AUTHOR]

Storing deterministic test data on-chip allows logic built-in self-test (LBIST) to produce a special type of random test that consists of random combinations of deterministic test data. Such tests can achieve a higher fault coverage than random tests whose bits are determined randomly. A bottleneck of this approach is the volume of test data that needs to be stored. This article observes that the use of multicycle tests can address this bottleneck by reducing the number of tests needed for detecting target faults and, thus, the volume of test data needed for producing them. A software procedure is described to support this solution. Experimental results for benchmark circuits demonstrate the effectiveness of multicycle tests in this context. [ABSTRACT FROM AUTHOR]

A test compaction procedure under transparent scan can compact a scan-based test set that contains a minimum number of tests. The additional test compaction can be important in applications that require highly compacted test sets. Transparent scan views a scan-based test set as a sequence of scan shift and functional capture cycles and allows the two types of clock cycles to appear in arbitrary sequences. The contribution of this brief is to suggest that one of the reasons for the effectiveness of transparent scan for test compaction is its ability to prepone fault detections by replacing scan shift with functional capture cycles when faults are activated during scan shift cycles. When fault detections are preponed, clock cycles around the original detection clock cycles become unnecessary and can be omitted. This view results in a new test compaction procedure that focuses on steps that contribute to test compaction, thus reducing the computational effort of test compaction compared with general-purpose test compaction procedures. [ABSTRACT FROM AUTHOR]

Functional test sequences are used as manufacturing tests to complement scan-based tests. Functional test sequences target defects in the functional logic of the circuit. However, they may fail because of defects in the scan logic that prevent the circuit from operating correctly in functional mode. It is advantageous to detect such defects by dedicated test sequences before attempting to apply functional test sequences. The computation of dedicated test sequences for faults in the scan logic is the topic of this brief. The procedure described in this brief accepts a pool of functional test sequences. It identifies subsequences from the pool that are effective for detecting faults in the scan logic while balancing their lengths. It then compacts the sequences to reduce their total length further. Experimental results for benchmark circuits demonstrate large variations among different circuits in the total length of the sequences and significant reductions in the total length for all the circuits considered. [ABSTRACT FROM AUTHOR]

Fail data is collected by a tester from faulty units to allow defect diagnosis to be carried out. The fail data describes the full output response of the unit. The volume of fail data that faulty units produce during volume diagnosis can exceed the tester memory capacity. Existing solutions stop the fail data collection for a faulty unit after sufficient fail data has been collected or modify the test set to produce less fail data. This article considers the format for storing fail data on the tester. This article suggests a hybrid approach, where full output responses are stored for some tests, and only pass/fail information is stored for the remaining tests. This article describes procedures based on diagnostic fault simulation to determine a subset of tests for which full output responses are needed and for adding new tests such that fewer tests in the extended test set would require full output responses. The experimental results for benchmark circuits demonstrate the reductions in fail data volume that can be achieved by a hybrid approach. [ABSTRACT FROM AUTHOR]

Two-cycle gate-exhaustive faults provide a comprehensive model for delay defects that are localized to gates (cells or subcircuits). However, the number of two-cycle gate-exhaustive faults can be excessive. Cell-aware faults are obtained by performing layout analysis of cells to select faults that are important to detect. This article suggests a complementary view of faults that are important to detect. Under this view, a two-cycle gate-exhaustive fault is important to detect if it can affect the circuit during functional operation. Such faults can be identified by generating functional broadside tests. To obtain unconstrained two-cycle tests, which are more compact and detect more faults than functional broadside tests, the article uses a test generation procedure that extracts test cubes from functional broadside tests, merges the test cubes into tests, and derives both broadside and skewed-load tests from the resulting test data. The procedure is iterative to allow a gradual increase in the number of tests and the number of detected two-cycle gate-exhaustive faults. Experimental results for benchmark circuits demonstrate the tradeoff explored by the procedure. [ABSTRACT FROM AUTHOR]

In a commonly used test data compression method, the on-chip decompression logic is based on a linear-feedback shift-register (LFSR), and compressed tests consist of seeds for the LFSR. A seed can be modified and used for applying several different tests. This reduces the input test data volume further than the basic test data compression method. In this context, this article introduces a new approach for applying several different tests based on every seed. The new approach pads a seed in different ways to obtain new seeds for LFSRs with more bits, all of which can be implemented by a single programmable LFSR. The advantage of using LFSRs with more bits is that they are effective in detecting more target faults, thus supporting test compaction together with a reduction in the input test data volume. The experimental results for benchmark circuits demonstrate these points. [ABSTRACT FROM AUTHOR]

A comprehensive test set targets faults of different types to ensure that defects of different types are detected. When test compaction is carried out for such a test set, it is advantageous if the compacted test set contains a compact test set for each fault type separately. In this case, if one (or more) of the fault types is found to be more important to detect, a compact test set for it can be extracted without further processing. This article describes the first test compaction procedure for transition and stuck-at faults, where by construction, the compact test set contains compact test sets for each fault type separately. The experimental results for benchmark circuits demonstrate the ability to compact a comprehensive test set under this condition. [ABSTRACT FROM AUTHOR]

Dynamic test compaction procedures use independent fault sets to guide the generation of compact test sets. In addition, a maximal independent fault set provides a lower bound on the number of tests, and can thus be used for evaluating the level of test compaction. This article notes that defect-aware, cell-aware, and gate-exhaustive faults have certain properties that can be used in the computation of independent fault sets. This article focuses on gate-exhaustive faults and the computation of a maximal independent fault set. The experimental results for benchmark circuits support the discussion. [ABSTRACT FROM AUTHOR]

The use of both broadside (launch-on-capture) and skewed-load (launch-on-shift) tests for delay faults results in increased delay fault coverage and better test compaction than the use of a single test type. Two-cycle broadside and skewed-load tests differ in the sequence of length two applied to the scan-enable input between the scan-in and scan-out operations of a test. Considering a circuit with a single clock domain, the question that this article attempts to answer is whether it is possible to generate a complete test set for transition faults where all the tests use the same scan-enable sequence of length three or more. The use of a single scan-enable sequence simplifies the test application process. Experimental results demonstrate that there is a significant number of benchmark circuits for which a test set with a single scan-enable sequence achieves the same transition fault coverage as a test set that consists of both broadside and skewed-load tests. For other benchmark circuits, a small loss in transition fault coverage compared with the use of both test types allows a single scan-enable sequence to be used. [ABSTRACT FROM AUTHOR]

Multicycle tests are useful for test compaction even when full scan allows single- or two-cycle tests to be used. To avoid sequential test generation, multicycle tests can use the test data (scan-in states and primary input vectors) from a single- or two-cycle test set, possibly modified to make it more suitable for multicycle tests. However, the modification process requires repeated fault simulation to prevent a loss of fault coverage. This brief observes that the need to modify test data results from the fact that tests are only extended forward to increase their numbers of clock cycles starting from their (modified) scan-in states. The brief observes further that extending tests backward is a more computationally efficient way of obtaining multicycle tests with modified test data. The brief defines a new type of multicycle test to increase the effectiveness of backward extension and describes a test compaction procedure based on backward and forward extension. It presents experimental results for gate-exhaustive faults, requiring large numbers of tests, in benchmark circuits. [ABSTRACT FROM AUTHOR]

Multicycle tests have several advantages including the ability to support test compaction. By extracting multicycle functional broadside tests from functional test sequences, it is possible to ensure functional operation conditions during the functional capture cycles between the scan operations of a test. The challenge that this article addresses is that the computational effort of extracting $l$ -cycle functional broadside tests from a functional test sequence increases linearly with $l$. Therefore, the computational effort of a test generation procedure that increases $l$ gradually to match $l$ to the circuit is quadratic in $l$. This makes it infeasible to consider large values of $l$ that are important for test compaction. To address this challenge the paper develops a partitioning procedure under which test extraction requires the same computational effort for every $l$. This article also describes a test generation procedure that is linear in $l$. Experimental results for transition faults in benchmark circuits demonstrate the importance of large values of $l$ for test compaction. [ABSTRACT FROM AUTHOR]

Fail data is collected on a tester to allow defect diagnosis to be carried out. The high volume of fail data that some faulty units produce, and the test application time, motivated the development of procedures for terminating the fail data collection process before it stores the entire fail data for a faulty unit. A procedure for modifying a test set to reduce the fail data volume it produces was developed to complement these approaches, but without considering the constraints of a test data compression method. This article describes a procedure for modifying a stored test set to reduce the fail data volume under a test data compression method where a linear-feedback shift-register is used for on-chip decompression. The constraints of the test data compression method affect the procedure in several important ways. The experimental results for benchmark circuits demonstrate the ability of the procedure to reduce the fail data volume by modifying a stored test set. [ABSTRACT FROM AUTHOR]

Using both broadside and skewed-load tests for delay faults provides a higher fault coverage and more compacted test sets. An earlier work showed that it is possible to share input test data between broadside and skewed-load tests, and thus reduce the input test data volume. This article develops an algorithm for computing stored tests that can be used for applying both broadside and skewed-load tests in the context of a specific test data compression method. Under this method, a programmable linear-feedback shift register is used for on-chip decompression. In the stored test data, a stored test consists of a seed and two primary input vectors. The seed determines the scan-in state of the applied broadside or skewed-load test as well as the additional scan-in vector required for a skewed-load test. In the algorithm developed in this article, stored tests are computed directly without first computing broadside or skewed-load tests. This avoids situations where the tests cannot be compressed or do not have common input test data. [ABSTRACT FROM AUTHOR]

A logic diagnosis procedure provides information about the defects that are present in a faulty unit as a set of candidate faults. To obtain smaller, and more accurate, sets of candidate faults, a diagnostic test generation procedure produces a test set that distinguishes fault pairs. This paper observes that large sets of candidate faults are obtained when multiple defects are present in a faulty unit, even if a diagnostic test set is used for logic diagnosis. This points to the possibility that fault pairs do not provide a complete set of targets for diagnostic test generation. This paper analyzes the conditions that cause a large set of candidate faults to be formed under a particular logic diagnosis procedure and suggests new targets for diagnostic test generation. The experimental results for benchmark circuits demonstrate that a diagnostic test set can be improved by adding diagnostic tests for the new targets. [ABSTRACT FROM AUTHOR]

Under broadcast scan, scan chains are partitioned into groups that receive the same scan-in values. This article considers, for the first time, the application of functional broadside tests under broadcast scan. This article provides a definition of a close-to-functional broadside test that is applicable under a broadcast scan configuration. The test is referred to as a group-functional broadside test. This article describes how a subset of group-functional broadside tests is obtained from a functional broadside test and discusses the proximity to functional operation conditions that a group-functional broadside test maintains. It also describes the generation of a group-functional broadside test set. The experimental results for transition faults in benchmark circuits explore the tradeoff between the level of test data compression, the proximity to functional operation conditions, and the transition fault coverage, by considering scan configurations with different numbers of scan chains. [ABSTRACT FROM AUTHOR]

Maintaining functional operation conditions during the application of scan-based tests is important for avoiding overtesting of delay faults. This issue has been considered for the functional capture cycles of scan-based tests, where the faults are typically detected. When scan shift cycles are used for fault detection, functional operation conditions are important during scan shift cycles as well. A transparent-scan sequence allows both types of clock cycles to be considered uniformly, allowing faults to be detected during functional capture as well as scan shift cycles. This article defines the concept of a globally functional transparent-scan sequence that maintains close-to-functional operation conditions during all its clock cycles. The procedure described in this article for computing globally functional transparent-scan sequences starts from a transparent-scan sequence that avoids scan shift cycles in order to maintain functional operation conditions. The procedure introduces scan shift cycles into the sequence in order to detect target faults. This process is guided by a transparent-scan sequence that is translated from a conventional scan-based test set and achieves the same fault coverage. Experimental results for benchmark circuits demonstrate the tradeoff between the proximity to functional operation conditions and the fault coverage achievable by the globally functional transparent-scan sequence. [ABSTRACT FROM AUTHOR]

A recent work showed that it is possible to transform a single-cycle test for stuck-at faults into a skewed-load test that detects the same stuck-at faults without performing logic or fault simulation. By using this transformation, it is possible to generate a compact skewed-load test set for stuck-at and transition faults. The advantage for test compaction is related to the fact that the test set contains a single test type. For cases where broadside tests are preferred over skewed-load tests, this article studies the possibility of transforming a single-cycle test into a broadside test, and generating a compact broadside test set for stuck-at and transition faults. This article addresses several challenges in order to achieve this goal without resorting to sequential test generation or state justification that have a high computational complexity. The experimental results for benchmark circuits demonstrate the levels of test compaction that can be achieved using small numbers of observation points. [ABSTRACT FROM AUTHOR]

Reverse order fault simulation and its variations provide a test compaction option with a low computational effort that is applicable even when test constraints or complex fault models preclude the application of other conventional test compaction procedures. This is the scenario considered in this brief. Reverse order fault simulation procedures remove unnecessary tests from a test set without otherwise modifying it. Reverse order fault simulation is typically applied once after the complete test set has been generated. This brief observes that when other test compaction procedures are not applied, forward-looking reverse order fault simulation sometimes yields a smaller test set if it is applied more often during the test generation process. However, applying it more often also increases the computational effort. This brief explains this phenomenon and describes a procedure that uses the new insights to improve the ability of forward-looking reverse order fault simulation to achieve test compaction at a reduced computational effort. The experimental results for benchmark circuits are presented to support the discussion. [ABSTRACT FROM AUTHOR]

Test sequences that do not use scan chains have several advantages as manufacturing tests. Test sequences can be produced by sequential test generation procedures, and static test compaction can be applied to reduce the length of the sequence without losing fault coverage. A typical sequential test generation procedure that produces a single test sequence concatenates test subsequences to form the test sequence. Existing static test compaction procedures ignore the construction of the sequence from subsequences and consider every test vector individually for omission. This brief introduces a broad-brush static test compaction procedure that considers entire subsequences for omission to achieve test compaction. As additional subsequences are concatenated, subsequences concatenated earlier may become unnecessary. The procedure described in this brief identifies this situation. The advantage of a broad-brush approach is a low computational effort, which is demonstrated by experimental results for benchmark circuits. [ABSTRACT FROM AUTHOR]

Excessive switching activity in the fault-free circuit can cause a fault-free circuit to fail because of increased delays. For the same reason, excessive switching activity in a faulty circuit can cause a delay fault to escape detection. This paper observes that the switching activity is higher in the presence of multiple delay faults with higher multiplicities (larger numbers of single faults that are present in the circuit together). The challenge in addressing multiple faults is related to their large number. This paper addresses this challenge by an iterative procedure that is applied to transition faults under a low-power broadside test set, and has two subprocedures: 1) the first subprocedure finds multiple transition faults with excessive faulty switching activity and 2) the second subprocedure modifies the test set so as to avoid excessive faulty switching activity for the faults found by the first subprocedure. With every additional iteration there are fewer multiple transition faults that exhibit excessive faulty switching activity. The experimental results for benchmark circuits demonstrate the levels of excessive faulty switching activity in the presence of multiple transition faults, and the possibility of reducing or even eliminating it after a small number of iterations. [ABSTRACT FROM AUTHOR]

This paper defines a new type of a low-power broadside test, called a reverse low-power broadside test, whose application requires design-for-testability logic. The unique feature of a reverse low-power broadside test is that it duplicates the switching activity during the second functional capture cycle of a given low-power broadside test, except that signal-transitions are reversed. Thus, the switching activity of a reverse low-power broadside test duplicates that of a low-power broadside test in every subcircuit and on every line individually. In addition, the reversed test detects different faults, and can thus increase the fault coverage of a low-power broadside test set. This paper studies the ability of reverse low-power broadside tests to increase the transition fault coverage in benchmark circuits considering functional broadside tests as well as low-power broadside tests that are not functional. [ABSTRACT FROM AUTHOR]

This study considers the compression of a type of close‐to‐functional broadside tests called boundary‐functional broadside tests when the on‐chip decompression logic consists of a linear‐feedback shift register (LFSR). Boundary‐functional broadside tests maintain functional operation conditions on a set of lines (called a boundary) in a circuit. This limits the deviations from functional operation conditions by ensuring that they do not propagate across the boundary. Functional vectors for the boundary are obtained from functional broadside tests. Seeds for the LFSR are generated directly from functional boundary vectors without generating tests or test cubes. Considering the tests that the LFSR produces, the seed generation procedure attempts to obtain the lowest possible Hamming distance between their boundary vectors and functional boundary vectors. It considers multiple LFSRs with increasing lengths to achieve test data compression. The procedure is structured to explore the trade‐off between the level of test data compression and the Hamming distances or the proximity to functional operation conditions. [ABSTRACT FROM AUTHOR]

Test data compression is based on storage of compressed tests and use of on-chip decompression logic for test application. Further reductions in the input test data volume are achieved by methods that apply several different tests based on every compressed test. This article makes the new observation that by keeping the same number of compressed tests and applying several different tests based on every compressed test, it is possible to improve the quality of the test set applied to the circuit. This article studies such an approach for path delay faults (PDFs) using a linear-feedback shift register (LFSR) as the decompression logic. Because of the nature of PDFs, targeting an extended subset of PDFs increases the confidence that important PDFs are detected. However, the benefit of detecting additional faults may not justify an increase in the number of stored tests. The approach suggested in this article is used for detecting an extended subset of target PDFs using the same set of LFSR seeds. Extra clocking of the LFSR is used for obtaining scan-in states for several new two-cycle tests based on the same seed. Experimental results for benchmark circuits demonstrate the effectiveness of this approach. [ABSTRACT FROM AUTHOR]

This paper describes a test compaction procedure that combines the advantages of using multicycle tests for test compaction with the advantages of using both broadside and skewed-load tests for increasing the fault coverage and achieving test compaction. The procedure is the first to combine these two concepts in a single procedure. The combination is made possible by a definition of a multicycle skewed-load test that is suggested in this paper, and complements the definition of a multicycle broadside test. Experimental results demonstrate the effectiveness of multicycle broadside and skewed-load tests in achieving test compaction for benchmark circuits. [ABSTRACT FROM AUTHOR]

Test compaction benefits from the use of multicycle tests that have several clock cycles between their scan-in and scan-out operations. For maximum benefit, primary output vectors should be observed during all the clock cycles between the scan operations of a multicycle test. This allows the test to detect all the faults whose fault effects reach the primary outputs, in addition to the ones whose fault effects are latched onto the flip-flops before the scan-out operation. However, for consistency with single-cycle tests for single stuck-at faults, or two-cycle tests for transition faults, only one primary output vector should be observed per test. This can be the last primary output vector of the test, as in the case of single-cycle and two-cycle tests, but other options are more useful, as demonstrated in this article. In particular, this article suggests that the primary output vector to be observed should be selected individually for every test. It also describes a static procedure for selecting a single primary output vector to observe individually for every test based on a given compact multicycle test set and a dynamic test compaction procedure that produces multicycle test sets with this property. [ABSTRACT FROM AUTHOR]

Functional test sequences can detect defects that are not detected by scan-based tests, but overall, achieve a lower gate-level fault coverage than scan-based tests. Design-for-testability (DFT) approaches for functional test sequences cause the sequences to deviate from functional operation conditions in arbitrary ways over the entire design. This paper introduces the concept of invisible-DFT as a DFT approach for functional test sequences, where the effects of activating the DFT logic are confined to selected logic blocks. This paper develops an invisible-scan approach. Considering a single logic block, the procedure described in this paper inserts scan shift cycles into a functional test sequence while maintaining the same primary input and output sequences for the logic block. This makes the activation of the DFT logic invisible to other logic blocks. The procedure allows a limited number of primary output vectors to be corrected for this purpose. Experimental results are presented to demonstrate the increase in fault coverage that can be achieved by invisible-scan. [ABSTRACT FROM AUTHOR]

Multicycle tests achieve test compaction by increasing the number of clock cycles between scan operations and reducing the number of tests. Tests in a compact multicycle test set typically have different numbers of clock cycles between their scan operations. This creates an opportunity to improve the test set by increasing the numbers of clock cycles between the scan operations of the tests, without increasing the number of tests and without exceeding a bound $L$ on the number of clock cycles. Motivated by this observation, this paper studies the padding of multicycle broadside and skewed-load tests for transition faults. After padding, all the tests have $L$ clock cycles between their scan operations. This paper makes several observations and defines new types of multicycle tests that are supported by commercial tools to allow padding to be performed without losing fault coverage. The new types of tests can be used for achieving a higher fault coverage, further test compaction, or an improved test set quality within the bound $L$. This paper develops padding procedures and presents experimental results for benchmark circuits to demonstrate these effects. [ABSTRACT FROM AUTHOR]

Test generation procedures target a variety of fault models in order to produce test sets that are effective for defect detection. This paper considers the likely scenario where two-cycle skewed-load tests are generated to detect single transition faults, and the test set is complemented with tests for single stuck-at faults that are not detected by the transition fault test set. For this scenario, this paper makes several unique observations that can be utilized to produce a single compact test set that consists only of two-cycle skewed-load tests for both fault models. The first observation is that a single-cycle test for a stuck-at fault can be transformed into a skewed-load test that is guaranteed to detect the stuck-at fault without performing logic or fault simulation. The second observation is that skewed-load tests, which are transformed from single-cycle tests for stuck-at faults, sometimes detect more transition and stuck-at faults than tests that were generated for transition faults. The third observation is that a static test compaction procedure, which is based on the modification and removal of tests, is effective in this context because it allows tests for stuck-at faults to detect more transition faults and vice versa. This paper describes a test compaction procedure based on these observations and presents experimental results for benchmark circuits to demonstrate the effectiveness of the procedure. [ABSTRACT FROM AUTHOR]

A comprehensive test set targets the detection of several fault models. As an example, in this study, stuck‐at faults, transition faults and four‐way bridging faults are targeted. Bridging faults represent a fault model where it is necessary to select a subset of target faults from all the possible faults. After test generation for single stuck‐at faults, undetectable single stuck‐at faults can be used for identifying undetectable transition and four‐way bridging faults. These faults can be removed from the sets of target faults to reduce the test generation effort. The new contribution of the study is related to the possibility of updating the set of target bridging faults again after test generation for transition faults. The analysis performed in the study leads to the premise that the presence of an undetectable or aborted transition fault on a line g makes bridging faults that are associated with line g less likely to be detected. As a result, line g may be covered by fewer bridging faults than selected for it, creating a test hole. To address this issue, the study suggests that more bridging faults should be selected for line g in this case. Experimental results are presented to support the discussion. [ABSTRACT FROM AUTHOR]

Transparent-scan is an approach to test compaction where scan shift cycles and functional capture cycles are interleaved in arbitrary ways as needed for detecting target faults. This is achieved by viewing the scan enable input as a regular primary input that can be assigned arbitrary sequences of zero and one values. This paper notes that transparent-scan leaves an unused combination of the scan enable and scan chain input values. This paper suggests that the unused combination can control design-for-testability logic to achieve better test compaction. At the cost of one additional EXCLUSIVE-OR gate for every state variable, and routing of the scan chain input to all the flip-flops, the extended transparent-scan approach described in this paper allows the values of the next-state variables to be complemented before they are latched in the flip-flops during a functional capture cycle. Extended transparent-scan is developed under bounded transparent-scan, where scan-in and scan-out operations of a conventional scan-based test set are maintained in order to limit the computational cost. Experimental results for transition faults in the functional logic of benchmark circuits demonstrate the additional test compaction that can be achieved with extended transparent-scan. Transition faults in the scan logic are considered as well. [ABSTRACT FROM AUTHOR]

In the initial stages of the yield improvement process for a new technology, a faulty unit may contain several defects (a multiple defect). The presence of a multiple defect may cause a state-of-the-art logic diagnosis procedure that is based on simulation and ranking of single modeled faults to produce a large set of candidate faults. Test removal or selection procedures are based on the observation that a large set of candidate faults is obtained when defects interact under certain tests. If the tests are ignored, the accuracy of logic diagnosis is improved. However, when a test is ignored, useful diagnostic information may also be lost. Instead, this brief suggests that it is possible to assign a score to every test based on its contribution to the accuracy of logic diagnosis. The test scores are used for scaling the contributions of the tests to the identification of candidate faults. This results in a reduced set of candidate faults where the faults are identified by tests with higher scores. The procedure requires a single additional logic diagnosis step, with a negligible computational effort. Experimental results are presented for multiple defects in benchmark circuits to demonstrate the effectiveness of the procedure. [ABSTRACT FROM AUTHOR]

Functional broadside tests avoid overtesting of delay faults that may occur with scan tests. Functional broadside tests can be extracted from a functional test sequence. This paper describes a procedure for extracting a close-to-minimum set of multicycle functional broadside tests from a functional test sequence. The procedure uses a modified sequential fault simulation process to collect information about detectable faults. This process indicates which faults must be detected by scan-out operations of multicycle tests, and which ones can be detected on primary outputs. The procedure uses a set-covering procedure to select a close-to-minimum set of clock cycles for scan-out operations. Every scan-out operation is complemented into a multicycle test. In addition, the procedure selects at most one test for faults that can be detected on the primary outputs. Experimental results are presented for benchmark circuits to demonstrate various features and extensions of the procedure. [ABSTRACT FROM AUTHOR]

Two challenges are combined when compressed tests are computed for path delay faults: 1) path delay faults that are important to detect are associated with long paths, and many of these faults are undetectable and 2) it may not be possible to compress a given test for a path delay fault. This paper addresses these challenges in the context of test data compression methods that are based on a linear-feedback shift-register (LFSR). The basic approach that this paper uses modifies initially random seeds for the LFSR into seeds that produce tests for detecting target faults. This approach can find seeds even if the available tests cannot be compressed into seeds. In addition, the procedure described in this paper also selects detectable path delay faults to address the presence of undetectable path delay faults in the set of target faults. For this purpose it uses a metric that measures the similarity between target and detected path delay faults, and attempts to compute seeds that increase the values of this metric. Experimental results are presented to demonstrate the ability of the procedure to detect path delay faults in benchmark circuits. [ABSTRACT FROM AUTHOR]

A diagnostic test generation procedure targets fault pairs in a set of target faults with the goal of distinguishing all the fault pairs. When a fault pair cannot be distinguished, it prevents the diagnostic test set from providing information about the faults, and consequently, about defects whose diagnosis would have benefited from a diagnostic test for the indistinguishable fault pair. This is referred to in this paper as a diagnostic hole. This paper observes that it is possible to address diagnostic holes by targeting different but related fault pairs, possibly from a different fault model. As an example, this paper considers the case where diagnostic test generation is carried out for single stuck-at faults, and related bridging faults are used for addressing diagnostic holes. Considering fault detection, an undetectable single stuck-at fault implies that certain related bridging faults are undetectable. This paper observes that, even if a pair of single stuck-at faults is indistinguishable, a related pair of bridging faults may be distinguishable. Based on this observation, diagnostic tests for pairs of bridging faults are added to a diagnostic test set when the related single stuck-at faults are indistinguishable. Experimental results of defect diagnosis for defects that do not involve bridging faults demonstrate the importance of eliminating diagnostic holes. [ABSTRACT FROM AUTHOR]

This brief describes a new approach to test compaction under transparent scan. Transparent scan achieves higher levels of test compaction than possible with the conventional scan-based tests by interleaving scan shift cycles and functional clock cycles in arbitrary ways. Earlier approaches relied on the computation of a single transparent-scan sequence, and the omission of test vectors from it. However, a single transparent-scan sequence can be prohibitively long. In the approach described in this brief, a transparent-scan test set consists of several sequences whose lengths are limited. Test compaction is achieved by combining sequences into longer sequences that detect more faults, and removing from the test set entire sequences that become unnecessary. Experimental results for benchmark circuits demonstrate the ability of the procedure to achieve test compaction without creating prohibitively long transparent-scan sequences. [ABSTRACT FROM AUTHOR]

Multicycle tests support test compaction by including several functional capture cycles in every test. However, even highly compacted multicycle test sets typically contain single-cycle or two-cycle tests for faults that cannot be detected using tests with larger numbers of clock cycles. An analysis of such tests reveals that the tests can be extended to include larger numbers of functional capture cycles if observation points are placed in the circuit. Moreover, the analysis shows that it is sufficient to place observation points on selected present-state or next-state variables. This is advantageous for the detection of delay faults without changing the paths they traverse. Based on this analysis, this brief describes a test compaction procedure for multicycle tests that places observation points on present-state variables in order to enable additional test compaction. Experimental results demonstrate the existence of cases where the observation points are effective in reducing the number of tests in a test set that is already highly compacted. [ABSTRACT FROM AUTHOR]

A simulation-based design verification process creates a large pool of functional test sequences. Such sequences have several advantages when they are used as manufacturing tests and for defect diagnosis. This brief considers the problem of selecting functional test sequences from a given pool when the goal is to use the sequences for defect diagnosis. The procedure described in this brief relies on the defect diagnosis of faulty units for the selection of sequences. Experimental results for simulated faulty units based on benchmark circuits demonstrate the possibility of learning from a limited set of faulty units which sequences from a given pool are effective for defect diagnosis. [ABSTRACT FROM AUTHOR]

This paper defines a new type of multicycle tests called autonomous multicycle tests. Similar to multicycle scan-based tests, autonomous multicycle tests include several consecutive functional capture cycles to enhance defect detection and achieve test compaction. Unlike multicycle scan-based tests, an autonomous multicycle test set uses the same initial state for all the tests. During the functional capture cycles of a test, the primary inputs are driven by primary outputs, and the circuit operates autonomously. A test uses a scan-in operation only for the initial primary input vector, and to determine the connection between the primary inputs and outputs. It uses a scan-out operation only for the final primary output vector. This results in reduced overheads related to storage requirements and test application time compared with scan-based tests, and several unique properties that are discussed in this paper. This paper describes a test generation procedure for autonomous multicycle tests that avoids sequential test generation, and presents experimental results to demonstrate the ability of the tests to detect target faults. [ABSTRACT FROM AUTHOR]

This study describes a static test compaction procedure that is applicable in the scenario where (i) a large pool of tests can be generated efficiently, but (ii) test compaction that modifies tests, and covering procedures, are not applicable, and (iii) reverse order fault simulation procedures are not sufficient for test compaction. The procedure has the ability to identify tests in the pool that are effective for test compaction even when they do not increase the fault coverage. This ability is achieved using only fault simulation with fault dropping. The procedure is designed for the case where multicycle functional broadside tests are extracted from functional test sequences. The use of multicycle tests results in higher levels of test compaction than possible with two‐cycle functional broadside tests. It adds another dimension to the procedure that also needs to select a number of clock cycles for every test. [ABSTRACT FROM AUTHOR]

Identical instances of a logic block are included in a design to improve its performance or reliability. This allows instances at close proximity to be tested by comparing their output responses, alleviating the need to know which tests will be applied, or what the fault-free response is. This paper considers an approach to online testing where the primary output sequences of identical finite-state machines that receive the same primary input sequences are compared to detect faults. To address the hardware and delay overheads of bringing one of the machines to the same state as the other before starting the output comparison process, this paper describes an initialization process where only part of the state of one machine is loaded into the other, and subsequences of their common primary input sequences are used for completing the initialization process. A unique feature of this process is that it addresses the situation where the input sequences that are applied during online testing, and the initial state for output comparison, are unknown. With this initialization process it is possible to start the output comparison process at an arbitrary point during functional operation. Experimental results for benchmark circuits demonstrate the percentages of state variables who values need to be loaded from one machine to the other, the fault coverage that can be achieved by output comparison following initialization, and the occurrence of failures in the initialization process. [ABSTRACT FROM AUTHOR]