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Cryogenic microsystems that utilize different 3D integration techniques are being actively developed, e.g., for the needs of quantum technologies. 3D integration can introduce opportunities and challenges to the thermal management of low temperature devices. In this work, we investigate sub-1 K inter-chip thermal resistance of a flip-chip bonded assembly, where two silicon chips are interconnected by compression bonding via indium bumps. The total thermal contact area between the chips is 0.306 mm2, and we find that the temperature dependence of the inter-chip thermal resistance follows the power law of α T − 3 , with α = 7.7 – 15.4 K4μm2/nW. The T − 3 relation indicates phononic interfacial thermal resistance, which is supported by the vanishing contribution of the electrons to the thermal conduction, due to the superconducting interconnections. Such a thermal resistance value can introduce a thermalization bottleneck in particular at cryogenic temperatures. This can be detrimental for some applications, yet it can also be harnessed. We provide an example of both cases by estimating the parasitic overheating of a cryogenic flip-chip assembly operated under various heat loads as well as simulate the performance of solid-state junction microrefrigerators utilizing the observed thermal isolation. [ABSTRACT FROM AUTHOR]

We demonstrate highly transparent silicon–vanadium and silicon–aluminum tunnel junctions with relatively low sub-gap leakage current and discuss how a trade-off typically encountered between transparency and leakage affects their refrigeration performance. We theoretically investigate cascaded superconducting tunnel junction refrigerators with two or more refrigeration stages. In particular, we develop an approximate method that takes into account self-heating effects but still allows us to optimize the cascade a single stage at a time. We design a cascade consisting of energy-efficient refrigeration stages, which makes cooling of, e.g., quantum devices from above 1 K to below 100 mK a realistic experimental target. [ABSTRACT FROM AUTHOR]

A thin, flat, and single crystal germanium membrane would be an ideal platform on which to mount sensors or integrate photonic and electronic devices, using standard silicon processing technology. We present a fabrication technique compatible with integrated-circuit wafer scale processing to produce membranes of thickness between 60 nm and 800 nm, with large areas of up to 3.5 mm2. We show how the optical properties change with thickness, including appearance of Fabry-Pérot type interference in thin membranes. The membranes have low Q-factors, which allow the platforms to counteract distortion during agitation and movement. Finally, we report on the physical characteristics showing sub-nm roughness and a homogenous strain profile throughout the freestanding layer, making the single crystal Ge membrane an excellent platform for further epitaxial growth or deposition of materials. [ABSTRACT FROM AUTHOR]

Electron–phonon interaction and electronic thermal conductivity have been investigated in heavily doped silicon at subKelvin temperatures. The heat flow between electron and phonon systems is found to be proportional to T[sup 6]. Utilization of a superconductor–semiconductor–superconductor thermometer enables a precise measurement of electron and substrate temperatures. The electronic thermal conductivity is consistent with the Wiedemann–Franz law. [ABSTRACT FROM AUTHOR]

We describe optical characterisation of a strained silicon cold electron bolometer (CEB), operating on a 350 mK stage, designed for absorption of millimetre-wave radiation. The silicon cold electron bolometer utilises Schottky contacts between a superconductor and an n++ doped silicon island to detect changes in the temperature of the charge carriers in the silicon, due to variations in absorbed radiation. By using strained silicon as the absorber, we decrease the electron-phonon coupling in the device and increase the responsivity to incoming power. The strained silicon absorber is coupled to a planar aluminium twin-slot antenna designed to couple to 160GHz and that serves as the superconducting contacts. From the measured optical responsivity and spectral response, we calculate a maximum optical efficiency of 50% for radiation coupled into the device by the planar antenna and an overall noise equivalent power, referred to absorbed optical power, of 1:1× 10-16WHz-1/2 when the detector is observing a 300K source through a 4K throughput limiting aperture. Even though this optical system is not optimized, we measure a system noise equivalent temperature difference of 6mKHz-1/2. We measure the noise of the device using a cross-correlation of time stream data, measured simultaneously with two junction field-effect transistor amplifiers, with a base correlated noise level of 300 pV Hz-1/2 and find that the total noise is consistent with a combination of photon noise, current shot noise, and electron-phonon thermal noise. [ABSTRACT FROM AUTHOR]

We report on fabrication and characterization of ultra-thin suspended single crystalline flat silicon membranes with thickness down to 6 nm. We have developed a method to control the strain in the membranes by adding a strain compensating frame on the silicon membrane perimeter to avoid buckling after the release. We show that by changing the properties of the frame the strain of the membrane can be tuned in controlled manner. Consequently, both the mechanical properties and the band structure can be engineered, and the resulting membranes provide a unique laboratory to study low-dimensional electronic, photonic, and phononic phenomena. [ABSTRACT FROM AUTHOR]

Enhanced electron cooling is demonstrated in a strained-silicon/superconductor tunnel junction refrigerator of volume 40 μm3. The electron temperature is reduced from 300 mK to 174 mK, with the enhancement over an unstrained silicon control (300 mK-258 mK) being attributed to the smaller electron-phonon coupling in the strained case. Modeling and the resulting predictions of silicon-based cooler performance are presented. Further reductions in the minimum temperature are expected if the junction sub-gap leakage and tunnel resistance can be reduced. However, if only tunnel resistance is reduced, Joule heating is predicted to dominate. [ABSTRACT FROM AUTHOR]

The authors investigate a wafer scale tunnel junction fabrication method, where a plasma etched via through a dielectric layer covering bottom Al electrode defines the tunnel junction area. The ex situ tunnel barrier is formed by oxidation of the bottom electrode in the junction area. Room temperature resistance mapping over a 150 mm wafer gives local deviation values of the tunnel junction resistance that fall below 7.5% with an average of 1.3%. The deviation is further investigated by sub-1 K measurements of a device, which has one tunnel junction connected to four arrays consisting of N junctions (N=41, junction diameter 700 nm). The differential conductance is measured in single-junction and array Coulomb blockade thermometer operation modes. By fitting the experimental data to the theoretical models, the authors found an upper limit for the local tunnel junction resistance deviation of ∼5% for the array of 2N+1 junctions. This value is of the same order as the minimum detectable deviation defined by the accuracy of the authors' experimental setup. [ABSTRACT FROM AUTHOR]

Energy flow rate in degenerate n-type silicon-on-insulator (SOI) film is studied at low temperatures. The electrons are heated above the lattice temperature by electric field and the electron temperature is measured via semiconductor–superconductor quasiparticle tunneling. The energy flow rate in the system is found to be proportional to T5, indicating that electron–phonon relaxation rate and electron–phonon phase breaking rate are proportional to T3. The electron–phonon system in the SOI film is in the “dirty limit” where the electron mean free path is smaller than the inverse of the thermal phonon wave vector. [Copyright &y& Elsevier]

We demonstrate significant modification of the electron-phonon energy loss rate in a many-valley semiconductor system due to lattice mismatch induced strain. We show that the thermal conductance from the electron system to the phonon bath in strained n+Si, at phonon temperatures between 200 and 480 mK, is more than an order of magnitude lower than that for a similar unstrained sample. [ABSTRACT FROM AUTHOR]

We investigate carrier transport in a single 22-nm-thick double-gate Si quantum well device, which has independent contacts to electrons and holes. Conductance, Hall density and Hall mobility are mapped in a broad double-gate voltage window. When the gate voltage asymmetry is not too large only either electrons or holes occupy the Si well and the Hall mobility shows the fingerprints of volume inversion/accumulation. At strongly asymmetric double-gate voltage an electric field induced electron-hole (EH) bilayer is formed inside the well. The EH drag resistance Rhe is explored at balanced carrier densities: Rhe decreases monotonically from 860 to 37 Ω when the electron and hole densities are varied between ∼0.4×1016 and 1.7×1016 m-2. [ABSTRACT FROM AUTHOR]

We used an ensemble Monte Carlo simulator to study both the dc and transient behavior of a double gate silicon-on-insulator transistor (DGSOI) operated as a velocity modulation transistor (VMT) and as a conventional field effect transistor (FET). Operated as a VMT, the DGSOI transistor provides switching times shorter than 1 ps regardless of the channel length, with a significant current modulation factor at room temperature. The same device operated as a FET provides much longer switching times which, in addition, increase with the channel length. [ABSTRACT FROM AUTHOR]

We report on detailed room-temperature transport properties of a 17 nm thick double-gate silicon-on-insulator (DGSOI) transistor. We find that when the electron gas is transferred between the top and the bottom of the silicon-on-insulator (SOI) layer by changing the gate bias symmetry (i.e., applying the gate biases in a push–pull fashion), while keeping the carrier density constant the maximum mobility occurs when the electron gas symmetrically occupies the whole SOI slab. The observed mobility behavior is the fingerprint of volume inversion/accumulation. This gate bias symmetry dependency of the mobility suggests that DGSOI devices intrinsically can be operated in a velocity modulation transistor (VMT) mode. In the experimental gate bias window, the maximum velocity/mobility modulation is ∼40%. The VMT transconductance exceeds conventional single-gate transconductance when electron density is above ∼5.3×1016 m-2. Improvements of the observed VMT operation in thin DGSOI devices are discussed. [ABSTRACT FROM AUTHOR]

Low temperature mobility measurements of silicon-on-insulator (SOI) metal-oxidefield-effect-transistors are reported. The batch of devices fabricated in this work includes both ultrathin and thick devices for which the SOI film thicknesses are in the ranges of 10–15 nm and 56–61 nm, respectively. The 4.2 K peak mobility of the thick devices is 1.9 m[sup 2]/V s. The ultrathin devices show mobility degradation at low electron densities where the mobility is also observed to decrease with decreasing the SOI film thickness. The peak mobilities of these devices are in the range of 1.35–1.57 m[sup 2]/V s. Numerical calculations show that ultrathin devices are in the limit where the electrons are confined by the quantum well defined by gate oxide and buried oxide, which is interpreted to lead to the observed mobility degradation. © 2004 American Institute of Physics. [ABSTRACT FROM AUTHOR]

We demonstrate significant cooling of electrons in a nanostructure below 10 mK by demagnetisation of thin-film copper on a silicon chip. Our approach overcomes the typical bottleneck of weak electron-phonon scattering by coupling the electrons directly to a bath of refrigerated nuclei, rather than cooling via phonons in the host lattice. Consequently, weak electron-phonon scattering becomes an advant- age. It allows the electrons to be cooled for an experimentally useful period of time to temperatures colder than the dilution refrigerator platform, the incoming electrical connections, and the host lattice. There are efforts worldwide to reach sub-millikelvin electron temperatures in nanostructures to study coherent electronic phenomena and improve the operation of nanoelectronic devices. On-chip magnetic cooling is a promising approach to meet this challenge. The method can be used to reach low, local electron temperatures in other nanostructures, obviating the need to adapt traditional, large demagnetisation stages. We demonstrate the technique by applying it to a nanoelectronic primary thermometer that measures its internal electron temperature. Using an optimised demagnetisation process, we demonstrate cooling of the on-chip electrons from 9 mK to below 5 mK for over 1000 seconds. [ABSTRACT FROM AUTHOR]

We report on stress induced changes in the dispersion relations of acoustic phonons propagating in 27 nm thick single crystalline Si membranes. The static tensile stress (up to 0.3 GPa) acting on the Si membranes was achieved using an additional strain compensating silicon nitride frame. Dispersion relations of thermally activated hypersonic phonons were measured by means of Brillouin light scattering spectroscopy. The theory of Lamb wave propagation is developed for anisotropic materials subjected to an external static stress field. The dispersion relations were calculated using the elastic continuum approximation and taking into account the acousto-elastic effect. We find an excellent agreement between the theoretical and the experimental dispersion relations. [ABSTRACT FROM AUTHOR]

Cooling of electrons in a heavily doped silicon by quasiparticle tunneling using a superconductor–semiconductor–superconductor double-Schottky-junction structure is demonstrated at low temperatures. In this work, we use Al as the superconductor and thin silicon-on-insulator (SOI) film as the semiconductor. The electron–phonon coupling is measured for the SOI film and the low value of the coupling is shown to be the origin of the observed significant cooling effect. © 2001 American Institute of Physics. [ABSTRACT FROM AUTHOR]

We demonstrate electron cooling in silicon using platinum silicide as a superconductor contact to selectively remove the highest energy electrons. The superconducting critical temperature of bulk PtSi is reduced from around 1 K to 0.79 K by using a thin film (10 nm) of PtSi, which enhances cooling performance at lower temperatures. We use an electron cooling model to infer that electrons in silicon are cooled from 100 mK to 50 mK in such a device. [ABSTRACT FROM AUTHOR]

We study the relaxation of coherent acoustic phonon modes with frequencies up to 500 GHz in ultrathin free-standing silicon membranes. Using an ultrafast pump-probe technique of asynchronous optical sampling, we observe that the decay time of the first-order dilatational mode decreases significantly from ~4.7 ns to 5 ps with decreasing membrane thickness from --194 to 8 nm. The experimental results are compared with theories considering both intrinsic phonon-phonon interactions and extrinsic surface roughness scattering including a wavelength-dependent specularity. Our results provide insight to under-stand some of the limits of nanomechanical resonators and thermal transport in nanostructures. [ABSTRACT FROM AUTHOR]

In silicon-on-insulator metal oxide semiconductor structures with a peak mobility of 25,000 cm2/V s a strong drop of the resistivity towards low temperature has been observed. This metallic effect can be fitted by a linear-in-T term, which can be interpreted with both, the ballistic interaction corrections and the temperature dependent screening of impurity scattering. At low temperature and density in addition a strong increase of the resistivity towards lower T was observed, which is attributed to the contact regions of the sample. [Copyright &y& Elsevier]