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The problem that this study addresses is to understand how microwave radiation is able to degrade genomic DNA of E. coli. In addition, a comparative study was made to evaluate the suitability of a high-throughput automated electrophoresis platform for quantifying the DNA degradation under microwave radiation. Overall, this study investigated the genomic DNA degradation of E. coli under microwave radiation using automated gel electrophoresis. To examine the viable organisms and degradation of genomic DNA under microwave exposure, we used three methods: (1) post-microwave exposure, where E. coli was enumerated using modified mTEC agar method using membrane filtration technique; (2) extracted genomic DNA of microwaved sample was quantified using the Qubit method; and (3) automated gel electrophoresis, the TapeStation 4200, was used to examine the bands of extracted DNA of microwaved samples. In addition, to examine the impacts of microwaves, E. coli colonies were isolated from a fecal sample (dairy cow manure), these colonies were grown overnight to prepare fresh E. coli culture, and this culture was exposed to microwave radiation for three durations: (1) 2 min; (2) 5 min; and (3) 8 min. In general, Qubit values (ng/µL) were proportional to the results of automated gel electrophoresis, TapeStation 4200, DNA integrity numbers (DINs). Samples from exposure studies (2 min, 5 min, and 8 min) showed no viable E. coli. Initial E. coli levels (at 0 min microwave exposure) were 5 × 108 CFU/mL, and the E. coli level was reduced to a non-detectable level within 2 min of microwave exposure. The relationships between Qubit and TapeStation measurements was linear, except for when the DNA level was lower than 2 ng/µL. In 8 min of microwave exposure, E. coli DNA integrity was reduced by 61.7%, and DNA concentration was reduced by 81.6%. The overall conclusion of this study is that microwave radiation had a significant impact on the genomic DNA of E. coli, and prolonged exposure of E. coli to microwaves can thus lead to a loss of genomic DNA integrity and DNA concentrations. [ABSTRACT FROM AUTHOR]

The effect of gain and embedding of amplifying cells (amp-cell) on the output power of power amplifiers (PAs) at high mm-wave frequencies is studied. This is the frequency range where matching loss becomes comparable with the gain of the amp-cell in most silicon technologies. By deriving power equations of embedded amp-cell, power contours are plotted in the gain plane and an optimum embedding is designed to maximize the output power for a desired gain. To showcase the theory, a high-frequency, high-power amp-cell, called matched cascode, is introduced and subsequently embedded to boost both power gain and output power. To increase the output power even further, a differential slot power combiner (SPC) is introduced and its equivalent circuit is analyzed. Finally, using the embedded matched cascode cell, and the SPC, a $2 \times 8$ PA is implemented in 65-nm bulk CMOS. It consumes 732 mW from 2.4-V supply voltage, with a maximum power-added efficiency (PAE) of 1.03%. The PA features a $P_{\text {sat}}$ and OP1dB of 9.4 and 6.3 dBm, respectively, at 200 GHz, and a maximum power gain of 19.5 dB. [ABSTRACT FROM AUTHOR]

A current mismatch compensation structure for SSPLL charge pump (CP) is proposed and implemented in a low-power 40.5GHz frequency synthesizer. Transistor’s channel-length-modulation (CLM) effect induces SSPLL loop gain distortion and decreases VCO control voltage (Vctrl) locking range (LR). The proposed compensated CP uses feedback loops to cancel the CLM effect and hence extends Vctrl LR from 0.50V to 0.75V under a 1V supply, without degrading SSPLL noise performance. As a result of the more efficient use of Vctrl range, VCO capacitor bank setup number is reduced from 10 to 7 to cover the same 10% total tuning range. Due to the low-power dividerless structure with sub-sampling lock detector (SSLD) for frequency acquisition, the SSPLL with the proposed compensated CP consumes only 9.5mW power with 192fs RMS jitter. [ABSTRACT FROM AUTHOR]

Presents information on the IMS 2021 focus sessions. [ABSTRACT FROM AUTHOR]

A new two-element phase-locked loop (PLL)-coupled array for the implementation of millimeter-wave (mm-wave) and subterahertz (sub-THz) phased arrays is presented. This architecture avoids using lossy phase shifter to create the required phase shift between the adjacent elements in a phased-array system. The required phase shift is generated by utilizing a dual nested loop PLL. The two PLL loops work together to stabilize the frequency and create the required phase shift. Moreover, it can be scaled simply by adding more unit cells to the architecture. A 112–121-GHz two-element phased array is designed and fabricated in a standard 65-nm CMOS process. It consumes 147-mW power and provides a phase shift of 46.7° ranging from 58.53° to 105.2° at 117 GHz. [ABSTRACT FROM AUTHOR]

An 8.8-mW, low-noise, 40.5-GHz frequency synthesizer is proposed. The synthesizer system consists of a subsampling phase-locked loop (SSPLL) with 100-MHz crystal reference, a 900-MHz high-frequency-reference (HFR) PLL, and a novel subsampling lock detector (SSLD). The SSLD keeps monitoring the locking status of the SSPLL by sampling the SSPLL output with the HFR 900-MHz reference and automatically controls the SSPLL for frequency acquisition if it loses lock or locks to a wrong 100-MHz harmonic. This is done without using a power-consuming divider-based frequency-locked loop in conventional SSPLL. Due to the relatively low-frequency operation and moderate noise requirement of HFR, as well as the low-power SSLD, the proposed system achieves low power consumption and jitter simultaneously. The measured results show 8.8-mW power consumption and 228-fs rms jitter with in-band and out-band phase noises of −96.6 dBc/Hz at a 1-MHz offset and −106.9 dBc/Hz at a 10-MHz offset, respectively. [ABSTRACT FROM AUTHOR]

In this article, we present a 438–479-GHz fully integrated 25-element radiator array source based on a scalable structure of coupled standing wave oscillator cells without extra loss and parasitics from coupling networks. The bandwidth is extended using a varactor-less frequency tuning method, and EIRP is improved by increasing the size of the array using the proposed scalable coupling method and maximizing the radiation directivity using a silicon lens in an optimized radiation setup. An analysis of the radiation directivity of a chip-lens setup is presented as well as the employed approach for enhancing EIRP by maximizing the directivity. The circuit is implemented in a 65-nm CMOS process and is measured to have 40.7 GHz/8.9% frequency tuning range. The chip consumes 0.38–2.34-W power (1.18 W at 459-GHz center frequency) from a 1.2-V supply voltage. The circuit provides a maximum of −1.8-dBm radiated power and 19.3-dBm EIRP at 448 GHz using a 12.5-mm radius silicon lens. The minimum measured phase noise at 10-MHz offset is −100.6 dBc/Hz. To the best of our knowledge, this article has the largest EIRP, radiated power, and bandwidth among fully integrated silicon-based coherent sources above 350 GHz. [ABSTRACT FROM AUTHOR]

This article presents a 230-GHz wideband harmonic voltage-controlled oscillator (VCO) with large output power based on a compact and low-loss structure of coupled standing wave oscillators. In order to boost the output power, oscillators are coupled together without adding extra passive loss to the circuit. Transistors with inductive drain impedances provide the necessary negative resistance to the oscillators while simultaneously acting as active variable capacitors for frequency tuning and generate the desired second-harmonic power through their nonlinearities. Transmission lines at the drains are responsible for creating the inductive impedance as well as coupling adjacent oscillators and routing and combining the output power. Therefore, the circuit has a compact structure that minimizes passive losses. A varactor-less frequency tuning scheme is used and allows for wideband operation without sacrificing the output power. In addition to oscillator coupling and minimizing the losses, the output power has been boosted by engineering the harmonic impedance that is seen by the transistors in the circuit. The prototype chip was implemented in a 65-nm CMOS process. The output power of the VCO covers 219–238 GHz frequency band (8.35% tuning range) and delivers 3.4-dBm maximum output power. The minimum measured phase noise is −105.8 dBc/Hz (at 10-MHz offset) while consuming 195 mW from a 1.5-V supply. [ABSTRACT FROM AUTHOR]

In this paper, a 0.34-THz $2\times 2$ phased array integrated circuit is presented, which demonstrates a new approach for implementing phased arrays in the millimeter-wave (mm-wave)/terahertz (THz) spectrum. The circuit structure consists of four unit standing wave oscillators. In each cell, fundamental frequency ($f_{0}$) and odd harmonics are systematically cancelled, while the desired fourth harmonics ($4f_{0}$) are combined and radiated by on-chip patch antennas. A phase-shifter-less mechanism is employed based on combining standing and traveling waves to create the required phase shift between the sources for beam steering. The transistors provide negative resistance to the circuit and generate the desired fourth harmonics through nonlinearity. Simultaneously, transistors are employed as active variable capacitors for varactor-less frequency tuning. The implemented phased array is capable of independent wideband frequency tuning and 2-D wide-angle beam steering. The circuit is fabricated in a 0.13- $\mu \text {m}$ SiGe BiCMOS process and is measured to have 52-GHz/15.1% frequency tuning range from 318 to 370 GHz and 128°/53° 2-D beam-steering angle. The chip consumes 310–640 mW power from a 1.5-V supply with −6.8-dBm maximum radiated power and minimum −93.1-dBc/Hz phase noise at 10-MHz offset. To the best of our knowledge, this paper has the largest bandwidth among fully integrated THz radiator/phased arrays as well as the widest angle beam steering among fully integrated THz phased arrays. [ABSTRACT FROM AUTHOR]

In this paper, the challenges of designing distributed amplifiers at frequencies close to $f_{\text {max}}$ of transistors are tackled. By using bandpass transmission lines, the maximum operation frequency of the distributed amplifier is increased compared to low-pass transmission lines. Moreover, a novel gain-boosted cascode structure with an internal feedback is employed to cancel a part of the loss in the input line and boost the bandwidth and the highest operation frequency of the amplifier. The proposed amplifier operates up to frequencies as high as 0.67 $f_{\text {max}}$ of the transistors. Two proof-of-concept prototypes are fabricated in a 0.13- $\mu \text{m}$ SiGe process with $f_{\text {max}}$ of 210 GHz. The first prototype shows an average gain of 14.4 dB from 52 to 142 GHz (bandwidth of 90 GHz at the center frequency of 97 GHz) while the second one achieves an average gain of 18.6 dB from 48 to 135 GHz (bandwidth of 87 GHz at the center frequency of 91.5 GHz). [ABSTRACT FROM AUTHOR]

After completing two years as Editors-in-Chief of this Transactions, it is a good time to say a few words on how this journal is accomplishing its mission of serving the microwave community. [ABSTRACT FROM AUTHOR]

Based on piecewise linear modeling of field-effect transistors, harmonic translations are deployed to analyze the fundamental limits for a maximum second-harmonic power generation for any given field-effect transistor. Optimum waveforms at the gate–source and drain–source terminals, which yield high second-harmonic power generation by the given transistor, are derived. Two oscillators are implemented in a TSMC 65-nm CMOS process. Transistors in these oscillators have optimum voltage waveforms at their terminals. Thus, they deliver a state-of-the-art second-harmonic output power while operating at relatively higher frequencies than related arts. One of the proposed oscillators has the maximum output power of 4.9 dBm and a peak dc-to-RF efficiency of 3% at 300 GHz. Each of the implemented oscillators occupies 0.16 mm2 of the chip area. [ABSTRACT FROM AUTHOR]

In this paper, we present a new architecture for implementation of millimeter-wave (mm-wave) and terahertz (THz) radiator arrays based on standing-wave properties. This structure is a continuous distributed coherent array that avoids lossy and parasitic coupling networks. Moreover, it can be scaled simply by extending the size of the structure and replicating the unit cell. The absence of coupling parasitics in addition to the unique characteristics of standing waves allows us to extend the tuning range without using varactors. The 0.34-THz four-element radiator array is designed and fabricated in a 130-nm SiGe BiCMOS process using microstrip transmission lines as the standing-wave mediums and on-chip patch antennas to radiate the desired fourth harmonic of the oscillation. The circuit was measured with no post processing or silicon lens and has 5.9% frequency tuning range (332.5–352.8 GHz) with less than 6-dB output power variation across the band. It consumes 425-mW power from 1.8-V supply and the radiated power is −10.5 dBm at center frequency with −98.2 dBc/Hz phase noise at 10-MHz offset frequency. [ABSTRACT FROM PUBLISHER]

Based on time-variant behavior of metal-oxide–semiconductor field-effect transistors in large-signal operations, harmonic translations and their mutual effects are analyzed. Large amplitudes at terminal voltages of these transistors push them into different regions of operation. In this paper, harmonic translations are derived as a result of such changes in operation region of transistors. Operation in triode region for a portion of oscillation cycle results in iterative harmonic translations between fundamental frequency and second harmonic. They boost each other constructively for significantly stronger oscillation, more second harmonic output power, and enhanced dc-to-RF efficiency. Based on this analysis, a 215-GHz signal source, implemented in a TSMC 65-nm CMOS LP is presented. The proposed oscillator achieves a maximum output power of 5.6 dBm and a dc-to-RF efficiency of 4.6%. The measured phase noise is −94.6 dBc/Hz at 1-MHz offset. The proposed oscillator occupies only 0.08 mm2 of chip area. [ABSTRACT FROM PUBLISHER]

A voltage controlled oscillator (VCO) incorporating a system of coupled oscillators with two active mode switching (AMS) blocks is presented. The AMS blocks excite the main VCOs to operate in two distinct frequency bands. An overlap between the two frequency bands has extended the tuning range of the VCO. By turning the AMS blocks off, low-loss and low-capacitance behaviors of these blocks result in wide tuning range and high harmonic output power at high millimeter-wave frequencies. On the other hand, by turning the AMS blocks on, their loss-canceling and capacitance-tuning behaviors yield to higher power and wider tuning range with a lower center frequency. By having sufficient frequency overlap between the two modes, the implemented VCO achieves record tuning range of 20.7% at 190.5 GHz with a maximum output power of –2.1 dBm. This tuning range is significantly higher than reported silicon-based VCOs with center frequencies higher than 120 GHz. [ABSTRACT FROM PUBLISHER]

In this paper, a general embedding is proposed to boost the power gain of any device to the maximum achievable gain ( G\max ), which is defined as the maximum theoretical gain of the device. Using a gain-plane based analysis, two linear-lossless-reciprocal embeddings are used to perform a movement from the coordinate of the transistor to the coordinate that corresponds to G\max . The proposed embedding is applied to a 10 \mu \textm common-source NMOS transistor, and the theoretical and simulation results are presented and compared. The properties of the embedded transistor are inspected, and the few issues in implementation are investigated and addressed. Finally, using the proposed general embedding, an amplifier is implemented in a 65 nm CMOS process with a measured power gain of 9.2 dB at 260 GHz, which is the highest frequency reported in any silicon-based amplifier. [ABSTRACT FROM AUTHOR]

A 300 GHz frequency synthesizer incorporating a triple-push VCO with Colpitts-based active varactor (CAV) and a divider with three-phase injection is introduced. The CAV provides frequency tunability, enhances harmonic power, and buffers/injects the VCO fundamental signal from/to the divider. The locking range of the divider is vastly improved due to the fact that the three-phase injection introduces larger allowable phase change and injection power into the divider loop. Implemented in 90 nm SiGe BiCMOS, the synthesizer achieves a phase-noise of –77.8 dBc/Hz (–82.5 dBc/Hz) at 100 kHz (1 MHz) offset with a crystal reference, and an overall locking range of 280.32–303.36 GHz (7.9%). [ABSTRACT FROM AUTHOR]

A highly efficient push–push voltage-controlled oscillator (VCO) with a new inductive frequency tuning topology for (sub) terahertz frequencies is presented. The tuning technique is based on a variable inductance seen at the emitter node of a base-degenerated transistor. The variable inductor exhibits high quality factor and high tuning range due to the tunable transistor transconductance via bias current. Fabricated in a 0.13-\mu\m SiGe BiCMOS process, the VCO achieves a tuning range of 3.5% and an output power of -7.2 dBm at 201.5 GHz. The dc power consumption of the VCO is 30 mW, resulting in a high dc to RF power efficiency of 0.6% and a figure of merit (FoMT) of -165, which is the highest FoM for any silicon-based VCO reported to date at this frequency range. To demonstrate the functionality of the tuning technique, three VCO prototypes at different oscillation frequencies, including one operating in the 222.7–229-GHz range, are implemented and measured. [ABSTRACT FROM PUBLISHER]

We introduce a novel frequency tuning method for high-power terahertz sources in CMOS. In this technique, multiple core oscillators are coupled to generate, combine, and deliver their harmonic power to the output node without using varactors. By exploiting the theory of nonlinear dynamics, we control the coupling between the cores to set their phase shift and frequency. Using this method, two high-power terahertz VCOs are fabricated in a 65 nm LP bulk CMOS process. The first one has a measured output power of 0.76 mW at 290 GHz with 4.5% tuning range and the output power of the second VCO is 0.46 mW at 320 GHz with 2.6% tuning range. The output power of these signal sources is 4 orders of magnitude higher than previous CMOS VCOs and is even higher than VCOs implemented in compound semiconductors with much higher cut-off frequencies. [ABSTRACT FROM AUTHOR]

In this paper, we study an electrical nonlinear medium consisting of voltage-dependent capacitors and inductors to generate sharp pulses from a lower frequency sinusoid. First, we analyze the optimum conditions for maximum harmonic generation in a uniform nonlinear line. Next, we extend the nonlinear line to a two-dimensional nonlinear lattice that is compatible with CMOS technology. Compared with the nonlinear line, the lattice relies on spatial power combining, higher cut-off frequency, and nonlinear wave interaction to enhance the pulse amplitude and sharpness. To show the feasibility of this method, we implement the first CMOS nonlinear lattice in a 0.13-\mum CMOS process, and successfully demonstrate 2.7-Vpp, 6.3-ps pulses from a 22-GHz input signal. [ABSTRACT FROM AUTHOR]

A wideband frequency multiplier that effectively generates and combines the even harmonics from multiple transistors is proposed. It takes advantage of standing-wave formation and loss cancellation in a distributed structure to generate high amplitude signals resulting in high harmonic power. Wide bandwidth operation and odd harmonic cancellation around the center frequency are the inherent properties of this frequency multiplier. Using this methodology, we implemented a frequency doubler that operates from 220 GHz to 275 GHz in a standard 65 nm CMOS process. Output power of -6.6 dBm (0.22 mW) and conversion loss of 11.4 dB are measured at 244 GHz. [ABSTRACT FROM AUTHOR]

A systematic approach to designing high frequency and high power oscillators using activity condition is introduced. This method finds the best topology to achieve frequencies close to the f\max of the transistors. It also determines the maximum frequency of oscillation for a fixed circuit topology, considering the quality factor of the passive components. Using this technique, in a 0.13 \mum CMOS process, we design and implement 121 GHz and 104 GHz fundamental oscillators with the output power of -3.5 dBm and -2.7 dBm, respectively. Next, we introduce a novel triple-push structure to realize 256 GHz and 482 GHz oscillators. The 256 GHz oscillator was implemented in a 0.13 \mum CMOS process and the output power of -17 dBm was measured. The 482 GHz oscillator generates -7.9 dBm (0.16 mW) in a 65 nm CMOS process. [ABSTRACT FROM PUBLISHER]

A new technique to design an inductorless transimpedance amplifier (TIA) is introduced. This technique uses N similar TIAs in parallel configuration to boost the overall bandwidth while keeping the transimpedance gain constant. Using this method, we design and implement a 10-Gb/s inductorless TIA with an active area of only 0.06 \mm^2 and a differential transimpedance gain of 62 \dB\Omega in a digital 0.13-\mu\m CMOS process. There is good agreement among the theory, simulation, and experimental results. [ABSTRACT FROM PUBLISHER]

A 2-D electrical filter is introduced that is compatible with today's conventional integrated circuit processes. The rich 2-D propagation properties of the medium are used to introduce a novel high quality factor filter called an electrical prism. The pro- posed filter shows a quality factor much larger than the quality factor of the individual components at high millimeter-wave and terahertz frequencies. This structure also provides a negative effective index in a low-pass LC lattice. Based on this idea, we show filters with quality factors of 130 at 230 GHz and 420 at 460 GHz consisting of elements with the quality factor of 10 and 20, respectively. The effect of component loss on the filter quality factor is discussed in this paper. The negative effective index and the filter behavior of the lattice is verified by measuring a prototype on a CMOS process at 32-40 GHz. There is good agreement among the theory, simulation, and experimental results. [ABSTRACT FROM AUTHOR]