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This work proposes an static random access memory (SRAM) with column-based split cell-VSS (CS-CVSS), data-aware write-assist (DAWA), and enhanced read sensing margin in 28-nm FDSOI technology. The proposed CS-CVSS and DAWA techniques improve both half-selected (HS) static noise margin (SNM) and write margin. They also improve HS dynamic noise margin (HS-DNM) by leveraging write through virtual ground with reduced load in the proposed write port. The proposed 3T read port enhances sensing margin by minimizing read bitline leakage through negative gate-to-source voltage regardless of cell data. A 16-kb 9T SRAM test chip demonstrated the minimum operating voltage for write and read operations as 0.47 and 0.25 V, respectively. The minimum energy of 6.72 pJ is achieved at 0.5 V. [ABSTRACT FROM AUTHOR]

Bias temperature instability (BTI) degradation poses increasingly critical lifetime reliability design challenges in static random access memory (SRAM), as fabrication technology marches toward a very deep nanometer regime. This paper presents circuit techniques that enable on-chip dynamic reliability management, which intelligently monitors and mitigates the half-selected cell stability failure due to BTI degradation in SRAM. The dynamic reliability management is achieved through the automated BTI-aware write word-line (WWL) control, whereby it detects the BTI degradation in SRAM cells through a replica row-based BTI-aware stability monitor and adjusts the WWL voltage level with two-phase write operation (TPWO). The WWL voltage level is divided into two phases to maintain the half-selected cell stability with BTI without compromising other circuit parameters. Silicon validation of a 16-kb SRAM based on a 28-nm fully depleted silicon on insulator (FDSOI) technology successfully demonstrates that the half-selected cell stability failure is eliminated from 57.13% down to 0% with the proposed approach at a marginal 3.42% power and 10% area overheads. [ABSTRACT FROM AUTHOR]

In sub/near-threshold operation, SRAMs suffer from considerable bitline swing degradation when the data pattern of a column is skewed to ‘1’ or ‘0’. The worst scenarios regarding this problem occur when the currently read SRAM cell has different data compared to the rest of the cells in the same column. In this work, we overcome this challenge by using a column-based randomization engine (CBRE). This CBRE circuit randomizes data stored to SRAM. This makes distribution of “1” and “0” in each column close to 50%, significantly increasing bitline swing. To further improve the bitline swing, we employ bitline boost biasing and dynamic bitline keeper schemes. Based on the mentioned techniques, we fabricated a 256 rows × 128 columns (32 Kb) 8T SRAM array in 65 nm CMOS technology. In our silicon measurement, the SRAM array shows successful 200 mV operation at room temperature, where energy consumption and access time are 1 pJ and 2.5 s, respectively. [ABSTRACT FROM PUBLISHER]

This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged to an intermediate level by a pulsed current source to minimize power. The proposed ABC scheme uses two dummy rows for digitally adjusting the pulse width and the delay of the sense amplifier enable signals of the CAM without disturbing the normal operation. Therefore, it can continuously track the optimum ML swing, making the CAM tolerant to variations. The proposed ABC scheme achieves the power reduction of 5.5× compared with the conventional ML sensing scheme. In addition, multi-V t transistors are used in the CAM cell to reduce the leakage by 15× while improving the ML discharging speed by 2× when compared with the standard-V t devices at 1.2 V, 80 °C. A test chip was prototyped using a standard 65 nm CMOS process. The average energy consumption is 0.77 fJ/bit/search at 1.2 V/500 MHz. [ABSTRACT FROM AUTHOR]

This brief presents a negative bias temperature instability (BTI)/positive BTI-aware write-wordline (WWL) voltage control technique for improving degraded cell stability of half-selected cells without extra power consumption. After BTI aging, the proposed lowering WWL voltage recovers the degraded cell stability without scarifying the write margin. Finally, we also present a sample circuit implementation of the proposed WWL voltage control scheme. [ABSTRACT FROM PUBLISHER]