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Dispatching a large number of dynamically changing requests directly to a small number of servers exposes the disparity between the requests and the machines. In this paper, we present a novel approach that dispatches requests to servers through virtual machines, called Dispatching Requests Indirectly through Virtual Environment (DRIVE). Client requests are first dispatched to virtual machines that are subsequently dispatched to actual physical machines. This buffering of requests helps to reduce the complexity involved in dispatching a large number of requests to a small number of machines. To demonstrate the effectiveness of the DRIVE framework, we set up an experimental environment consisting of a PC cluster and four benchmark suites. With the experimental results, we demonstrate that the use of virtual machines indeed abstracts away the client requests and hence helps to improve the overall performance of a dynamically changing computing environment. Copyright © 2009 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In this paper, a heterogeneous 3D-media processor is presented, which supports all 3-D display applications by combining a 3-D display IP with a 3-D graphics IP and a stereo video decoder. For mobile environments, adaptive power management scheme is proposed, which saves power consumption up to 186 mW by turning off idle functional blocks based on a target application, a target performance, and the run-time ratio between different IPs. As a result, the minimum power consumption of the processor is only 15 mW, while the overall power consumption is 201 mW. As well as the reduction of power consumption, this work shows impressive performance improvement. The proposed fast modulo operators and adopted division-free algorithm reduces the critical latencies of 3-D display image processing. The proposed fast datapath with parallel architecture increase synthesis rate up to 116 fps which is 17 times faster than a previous work. In addition, reordered operation sequence fixes memory bandwidth regardless of the number of images to be produced. In the 3-D graphics IP and the decoding IP, redundant datapath are merged using an IEEE 754 compliant floating-point vector unit to save both chip area and power consumption, which even reduces the critical latency by 30%. [ABSTRACT FROM AUTHOR]

In this paper, a power efficient vertex processor for mobile graphics applications is presented. A four-threaded and four-issue expanded VLIW datapath with a quad-float vertex texture fetcher is proposed by exploiting graphics specific characteristics after evaluation of several candidate architectures. Instruction-level power control methods such as operand sharing and writeback re-allocation along with operand isolations and gated clocks result in 40.4% and 82% reduction in energy dissipation and energy delay product compared to the most widely used single threaded SIMD. The proposed processor with the optimized datapath and vertex caches implemented in a 0.18-μm 1P4M CMOS process achieves 186-Mvertices/s geometry performance which is the best result among the processors that are IEEE-754 compliant. [ABSTRACT FROM AUTHOR]

In this paper, a 3-D display processor embedding a programmable 3-D graphics rendering engine is proposed. The proposed processor combines a 3-D graphics rendering engine and a 3-D image synthesis engine to support both true realism and interactivity for the future multimedia applications. Using high coherence between 3-D graphics data and 3-D display inputs, both pipelines are merged by sharing buffers such that a 3-fl display engine directly uses the output of a 3-D graphics rendering engine. The merged architecture has synergetic coupling effects such as freely providing various rendering effects to 3-fl images and easily computing disparities without complex extraction processes. In the 3-fl image synthesis engine, we adopt view interpolation algorithm and propose real-time synthesis method, pixel-by-pixel process. The view interpolation algorithm reduces the number of images to be rendered, resulting in the reduction of external memory size to 64.8% compared to conventional synthesis process. The proposed pixel-by-pixel process synthesizes 3-D images at 36 fps through bandwidth reduction of 26.7% and decreases internal memory size to 64.2% compared to typical image-by-image process. The 3-fl graphics rendering engine is programmable and supports the instruction sets of the latest 3-D graphics standard APIs, Pixel Shader 3.0 and OpeIIGLIES 2.0. The die contains about L7M transistors, occupies 5 mm x 5 mm in 0.18 ඵzm CMOS and dissipates 379 mW at 1.85 V. [ABSTRACT FROM AUTHOR]

In this paper, a 3-D vertex processor with a floating- point four-threaded and four-issue expanded VLIW architecture and vertex caches for mobile multimedia applications is proposed. The multi-threaded datapath prevents data hazards, and the multi-issue expanded VLIW architecture enables the processor to have an opportunity to execute instructions in parallel and a well-balanced way. The efficient vertex caches are proposed and implemented for the embedded vertex processors to accelerate its geometry operations and to save bandwidth between hosts and vertex processors. The proposed architecture with the vertex caches reduces the average total energy dissipation of 44.7% compared to a conventional single-threaded SIMD architecture, and the proposed vertex processor achieves 120 Mvertices/s of geometry performance which is 3.3 times faster than the previous result, and it supports OpenGL ES 2.0 and Vertex Shader Model 3.0. The processor is implemented in a 0.18-µm 1P4M CMOS process, and the operating frequency is 100 MHz. [ABSTRACT FROM AUTHOR]

A high-speed three-dimensional (3-D) graphics SoC for consumer applications is presented. A 166-MHz 3-D graphics full pipeline engine with performance of 33 Mvertices/s and 1.3 Gtexels/s, and 333-MHz ARM11 RISC processor, and video composition IPs are integrated together on a single chip. The geometry part of 3-D graphics IP provides full programmability in vertex and triangle level, and two-level multi-texturing with trilinear MIPMAP filtering are realized in the rasterization part. Per-pixel effects such as fog effects, alpha blending, and stencil test are also implemented in the proposed 3-D graphics IP. The rasterization architecture is designed for reducing external memory accedes to achieve the peak performance. The chip is fabricated using 0.13 μm CMOS technology and its area is 7.1 ⊗ 7.0 mm². [ABSTRACT FROM AUTHOR]