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In recent years, wireless sensor networks (WSN) have been considered for various aeronautical applications to perform sensing, data processing and wireless transmission of information, without the need to add extra wiring. However, each node of these networks needs to be self-powered. Considering the critical drawbacks associated with the use of electrochemical energy sources such as narrow operating temperature range and limited lifetime, environmental energy capture allows an alternative solution for long-term, deploy and forget, WSN. In this context, thermoelectricity is a method of choice considering the implementation context. In this paper, we present hands-on experience related to on-going implementations of thermoelectric generators (TEG) in airliners. In a first part, we will explain the reasons justifying the choice of ambient energy capture to power WSN in an aircraft. Then, we will derive the general requirements applying to the functional use of TEG. Finally, in the last section, we will illustrate the above issues through practical implementations.

This paper focuses on the process fabrication of a partial silicon-on-insulator (SOI) substrate for mixed power integration (low and high voltage devices on the same chip) at low cost. More specifically, such application would require a silicon substrate having localized thick SOI patterns associated with lateral isolation for control modules and bulk areas for power devices. The Lateral Epitaxial Growth over Oxide process (LEGO) based on fusion and recrystallization of polysilicon patterns, is a solution to obtain such a substrate at low cost and with a good SOI layer crystalline quality. A brief description of LEGO together with experimental results of LEGO process optimisation are presented.

The main feature of the thermomigration of Al/Si liquid droplets in silicon for the realization of isolation walls in bi-directional power devices is its low thermal budget. Therefore, it is compatible with the utilization of epitaxial substrates for innovative power devices, for example, with reduced on-state resistance. This paper describes the design and realization of a medium power SCR on epitaxy. After structure presentation and voltage blocking capability simulation, the specific issue of thermomigration on (1 1 1)-orientated epitaxial substrates is considered. Limitations to migration are found due to the off-axis cut necessary for good epitaxial growth. Electrical characterization exhibits great agreement with simulation, demonstrating the great potential of thermomigration as a low thermal budget technique for isolation walls processing for both standard structures and new devices on epitaxy.

A model, using geometric optics, has been developed to calculate the illumination of a wafer inside a rapid thermal processor. The main parameters of the model are: the processing chamber geometry, the lamp number and location, the reflector characteristics, and the wafer temperature. Each incident light component, i.e., direct or reflected, is identified, its contribution to the illumination of the wafer is calculated through a 3D analytical model, and the corresponding contour maps are depicted. Then, the heat diffusion equation is numerically solved in two dimensions, and thermal maps of a Si wafer are given versus various experimental conditions, such as the effect of patterning the reflectors, of individually adjusting the electrical power applied to each lamp, and the impact of rotating the wafer or using crossed lamp banks. The latter method, while being easy to implement, is shown to give excellent thermal uniformity. >

The reflectivity of thin‐film platinum silicide was measured by means of a helium‐neon (He‐Ne) laser when samples of platinum films deposited on top of silicon wafers were annealed in a rapid thermal processor. This processor consists of two rows of tungsten‐halogen quartz lamps placed above and below a quartz processing chamber. The thermal cycles consisted of a fast heating (about 200 °C/s), followed by an isothermal plateau at temperatures ranging between 410 and 600 °C. Film reflectivities dropped in two stages, as a result of the reaction between platinum and silicon. This two‐stage drop was identified as due to the transformation of the platinum film, first into Pt2Si, and then into PtSi. The amounts of time required to complete the transformations were found to be in good agreement with the Arrhenius laws derived from the work of J. T. Pan and I. A. Blech [Thin Solid Films 113, 129 (1984)] on isothermal low‐temperature (220–330 °C) sintering of platinum films on silicon, who unambiguously establish...