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In this paper, we demonstrate a clear gap in board level test coverage under category of timing related faults (TRFs). Although there are techniques that are capable to detect TRFs, there is no fault coverage metrics to quantify the quality of these techniques. To do that, we propose an easy-to-implement interconnect-level fault model extension towards TRFs. This extension can be integrated into existing test coverage models providing additional information on coverage of timing-related faults.

This paper presents a method for optimization of board-level scan test with the help of reconfigurable scan-chains (RSCs) implemented in a programmable logic of FPGA. Despite that the RSC concept is a well-known solution for scan-based test time reduction, the usage of RSC may lead to un-acceptable hardware overhead. In our work, we are targeting a completely new approach of exploiting on-board FPGA resources that being unconfigured are typically available during the manufacturing test phase for carrying out tests using temporarily implemented virtual RSC structures. As the allocated FPGA logic is re-claimed for functional use after the test is finished, the presented method delivers all the advantages of RSCs at no extra hardware cost. Experimental results show that the proposed virtual RSCs can fit into all available commercial FPGAs providing a significant test time reduction in comparison with state-of-the-art Boundary Scan test tecnique.