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In field-effect transistors, a semiconducting channel is indispensable for device switching. Here, the authors demonstrate semiconductor-less switching via modulation of the field emission barrier height across a graphene-hBN interface with ON/OFF ratio of 106.

The recent report of a p-type graphene(Gr)/carbon-nanotube(CNT) barristor facilitates the application of graphene barristors in the fabrication of complementary logic devices. Here, a complementary inverter is presented that combines a p-type Gr/CNT barristor with a n-type Gr/MoS2 barristor, and its characteristics are reported. A sub-nW (~0.2 nW) low-power inverter is demonstrated with a moderate gain of 2.5 at an equivalent oxide thickness (EOT) of ~15 nm. Compared to inverters based on field-effect transistors, the sub-nW power consumption was achieved at a much larger EOT, which was attributed to the excellent switching characteristics of Gr barristors.

The possibility to combine planar and van der Waals heterostructures holds great promise for nanoscale electronic devices. Here, the authors report an innovative method to synthesise embedded graphene quantum dots within hexagonal boron nitride matrix for vertical tunnelling single electron transistor applications.

We investigated the tunneling of graphene/insulator/metal heterojunctions by revising the Tsu–Esaki model of Fowler–Nordheim tunneling and direct tunneling current. Notably, the revised equations for both tunneling currents are proportional to V3, which originates from the linear dispersion of graphene. We developed a simulation tool by adopting revised tunneling equations using MATLAB. Thereafter, we optimized the device performance of the field-emission barristor by engineering the barrier height and thickness to improve the delay time, cut-off frequency, and power-delay product.

Microstructural control during the solution processing of small-molecule semiconductors (namely, soluble acene) is important for enhancing the performance of field-effect transistors (FET) and sensors. This focused review introduces strategies to enhance the gas-sensing properties (sensitivity, recovery, selectivity, and stability) of soluble acene FET sensors by considering their sensing mechanism. Defects, such as grain boundaries and crystal edges, provide diffusion pathways for target gas molecules to reach the semiconductor-dielectric interface, thereby enhancing sensitivity and recovery. Representative studies on grain boundary engineering, patterning, and pore generation in the formation of soluble acene crystals are reviewed. The phase separation and microstructure of soluble acene/polymer blends for enhancing gas-sensing performance are also reviewed. Finally, flexible gas sensors using soluble acenes and soluble acene/polymer blends are introduced, and future research perspectives in this field are suggested.

The original version of this Article contained an error in the spelling of the author Matthew Holwill, which was incorrectly given as Mathew Holwill. This has now been corrected in both the PDF and HTML versions of the Article.

Ethylenediamine-modified β-cyclodextrin (Et-β-CD) was immobilized on aggregated silver nanoparticle (NP)-embedded silica NPs (SiO2@Ag@Et-β-CD NPs) for the effective detection of flavonoids. Silica NPs were used as the template for embedding silver NPs to create hot spots and enhance surface-enhanced Raman scattering (SERS) signals. Et-β-CD was immobilized on Ag NPs to capture flavonoids via host-guest inclusion complex formation, as indicated by enhanced ultraviolet absorption spectra. The resulting SiO2@Ag@Et-β-CD NPs were used as the SERS substrate for detecting flavonoids, such as hesperetin, naringenin, quercetin, and luteolin. In particular, luteolin was detected more strongly in the linear range 10-7 to 10-3 Mthan various organic molecules, namely ethylene glycol, β-estradiol, isopropyl alcohol, naphthalene, and toluene. In addition, the SERS signal for luteolin captured by the SiO2@Ag@Et-β-CD NPs remained even after repeated washing. These results indicated that the SiO2@Ag@Et-β-CD NPs can be used as a rapid, sensitive, and selective sensor for flavonoids. [ABSTRACT FROM AUTHOR]

We report a new strategy to selectively localize and control microtubule translocation via electrical control of microtubules using a microfabricated channel on a functionalized-graphene electrode with high transparency and conductivity. A patterned SU-8 film acts as an insulation layer which shields the electrical field generated by the graphene underneath while the localized electric field on the exposed graphene surface guides the negatively charged microtubules. This is the first report showing that functionalized graphene can support and control microtubule motility. [ABSTRACT FROM AUTHOR]

With the motivation of realizing an all graphene-based circuit for low power, we present a reliable nonvolatile graphene memory device, single-layer graphene (SLG) ferroelectric field-effect transistor (FFET). We demonstrate that exfoliated single-layer graphene can be optically visible on a ferroelectric lead-zirconate-titanate (PZT) substrate and observe a large memory window that is nearly equivalent to the hysteresis of the PZT at low operating voltages in a graphene FFET. In comparison to exfoliated graphene, FFETs fabricated with chemical vapor deposited (CVD) graphene exhibit enhanced stability through a bi-stable current state operation with long retention time. In addition, we suggest that the trapping/de-trapping of charge carriers in the interface states is responsible for the anti-hysteresis behavior in graphene FFET on PZT. [ABSTRACT FROM AUTHOR]

Stability degradation in bottom-gate graphene field-effect transistors prepared by using inductively coupled plasma-chemical vapor deposition method are investigated under bias, temperature and illumination stress. The stretched-exponential time dependence model, which can be derived based on the trapping/detrapping of charges to/from existing traps and continuous redistribution of charges in bulk dielectrics, is well applied in fitting the time dependence of the transfer curve shifts in all stress conditions. The stress wavelength is considered as important factors as well as the bias and temperature stress in the transfer characteristic instabilities of graphene FEFs. [ABSTRACT FROM AUTHOR]

Device instabilities of graphene metal-oxide-semiconductor field effect transistors such as hysteresis and Dirac point shifts have been attributed to charge trapping in the underlying substrate, especially in SiO2. In this letter, trapping time constants around 87 μs and 1.76 ms were identified using a short pulse current-voltage method. The values of two trapping time constants with reversible trapping behavior indicate that the hysteretic behaviors of graphene field effect transistors are due to neither charge trapping in the bulk SiO2 or tunneling into other interfacial materials. Also, it is concluded that the dc measurement method significantly underestimated the performance of graphene devices. [ABSTRACT FROM AUTHOR]

Cobalt–polypyrrole(PPy)–cobalt nanowires were fabricated electrochemically in single-wire form inside anodic aluminum oxide templates. These wires were isolated by dissolving the template with chromic acid. Grown cobalt segments at both ends reveal a polycrystalline structure of a hexagonal-closest-packed structure and their [001] directions are 16° off the wire axis. By patterning a gate on one side of the wire, field-effect transistors (FETs) were produced. The measured output and transfer characteristics are as good as or better than film FETs of PPy. The gain of the wire FET could be controlled with successive electrochemical doping of the PPy segment. [ABSTRACT FROM AUTHOR]

The evolution of surface cleanliness and the electronic properties-Dirac voltage(VDirac), hysteresis and mobility (μ) of a graphene field-effect transistor (GFET)—were monitored by measuring lateral force microscopy and drain current (ID) as a function of gate voltage (VG), after mechanically cleaning the surface, scan-by-scan, with contact-mode atomic force microscopy. Both the surface cleanliness and the electronic properties evolved, showing a sudden improvement and then saturation for a mobility of around 2200 cm2 V−1 s−1. We found that the mobility suppression of the as-fabricated GFET deviated from a randomly distributed impurities model, which predicted a greater mobility than obtained from the measured VDirac. Therefore, the substrate impurities are excluded from the origins of the extraordinary suppression of the mobility, and the possible origin will be discussed. [ABSTRACT FROM AUTHOR]

Power amplifier circuits are implemented with graphene field-effect transistors (FETs), capacitors and inductors, and their gain is improved step-by-step by adjusting the passive components. The transistors are fabricated on a 150-mm wafer using conventional complementary-metal-oxide semiconductor processing along with graphene transferring processes. The completed circuit is implemented on a printed circuit board, which allows for adjustment of the external capacitance and inductance to study the performance of graphene RF FETs. A maximum signal gain of 1.3 dB is achieved at 380 MHz. The device parameters of the transistors are then extracted and the gain is analyzed, and the results show that lowering the source-drain conductance and gate resistance is the key in realizing high performance circuits. [ABSTRACT FROM AUTHOR]

Despite several years of research into graphene electronics, sufficient on/off current ratio /on//off in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier "barristor" (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 105) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier's height to be tuned to 0.2 electron volt by adjusting graphene's work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits. [ABSTRACT FROM AUTHOR]