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Carbon nanotubes (CNTs), are safe, biocompatible, bioactive, and biodegradable materials, and have sparked a lot of attention due to their unique characteristics in a variety of applications, including medical and dye industries, paper manufacturing and water purification. CNTs also have a strong film-forming potential, permitting them to be widely employed in constructing sensors and biosensors. This review concentrates on the application of CNT-based nanocomposites in the production of electrochemical sensors and biosensors. It emphasizes the synthesis and optimization of CNT-based sensors for a range of applications and outlines the benefits of using CNTs for biomolecule immobilization. In addition, the use of molecularly imprinted polymer (MIP)-CNTs in the production of electrochemical sensors is also discussed. The challenges faced by the current CNTs-based sensors, along with some the future perspectives and their future opportunities, are also briefly explained in this paper. RESEARCH HIGHLIGHTS: Review article on advanced Carbon-Nanotube (CNT)-based sensors and biosensors. The advantages of using CNTs for biomolecule immobilization and in electrochemical sensors and biosensors are discussed. The use of molecularly imprinted polymer-CNT nanocomposites in the production of electrochemical sensors is also discussed. Several characteristics, including sensor manufacturing, linear ranges, detection limits, and repeatability, are described in depth. Challenges and prospects using CNTs modified sensors have been proposed. [ABSTRACT FROM AUTHOR]

This letter presents a fully differential CMOS bootstrap rectifier with an effective dynamic threshold voltage (i.e., ${V}_{\text{TH}}$) compensation (DVC). The bootstrapping circuit for DVC, which consists of a dynamically biased transistor, a series resistor, and a parallel capacitor, dynamically generates a compensation voltage for the main rectifying pass transistors only when the ${V}_{\text{TH}}$ compensation is required. It significantly increases the proposed rectifier's power conversion efficiency (PCE) compared to other bootstrap rectifiers. The proposed rectifier operates at an industrial, scientific, and medical (ISM) band frequency of 434 MHz, and it is fabricated in a 0.18- $\mu$ m CMOS process together with two conventional bootstrap rectifiers for performance comparison. Measurement results validate that the proposed rectifier outperforms the conventional bootstrap rectifiers in terms of the output dc voltage level, voltage conversion ratio, and PCE. The proposed rectifier attains a peak PCE of 71 $\%$ at a load resistor of 3 k $\Omega$ and an operating frequency of 434 MHz. [ABSTRACT FROM AUTHOR]

This article presents a neural-recording IC with automatic gain control (AGC) according to the input signal level. AGC enhances the dynamic range (DR) of the recording IC by more than 30 dB and allows it to take the benefits of the front-end amplification-based and direct-conversion-based recording structures concurrently. By adaptively controlling the analog front-end (AFE) gain, the input-referred noise (IRN) of the overall system is greatly reduced while ensuring a wide DR. A continuous-time (CT) dynamic-zoom $\Delta \Sigma $ ADC (CT-Zoom-ADC) is used for power-efficient two-step conversion. The coarse conversion output is reused for AGC, and the fine conversion resolution is adjusted adaptively by modifying the oversampling ratio according to the varying AFE gain. The presented neural-recording IC achieves 99.5-dB DR and 6.1- $\mu \text{V}_{\textrm {rms}}$ IRN over 5-kHz bandwidth, resulting in FoMDR of 185.2 dB, the effective number of bits (ENOB) of 11.4 bits, and tolerance against artifacts with differential voltage amplitudes up to 1.6 $\text{V}_{\text {pp}}$. Measurements with pulsatile artifacts and experiments in vivo validate that the proposed IC is applicable to the closed-loop neural interface. [ABSTRACT FROM AUTHOR]

This paper presents an intra-body power transfer (IBPT) system that can deliver power greater than 1 mW across an on-body distance of 160 cm. A system simulation model is built for the characterization of the channel and optimization of the power transfer. Our system analysis and experimental validation demonstrate that 1 MHz is an optimal carrier frequency for IBPT in terms of power delivered to the load (PDL) and power efficiency (PE). Prototype TX and RX boards were built, and an IC was fabricated in a 180-nm CMOS process for the RX. The proposed RX IC consists of a voltage doubler (VD) and a charge pump (CP) to obtain a sufficiently high voltage conversion ratio (VCR). Among various rectifier topologies, the VD is the optimal topology for the power receiver front-end because the parasitic ground coupling capacitances, which inevitably exist in the IBPT system, act as an inherent input-coupling capacitance for the VD. The implemented VD utilizes a dynamic $V_{TH}$ compensation (DVC) for its diode components. Compared to the conventional static $V_{TH}$ compensation (SVC), DVC in the VD reduces the reverse leakage current of the diode, thus maximizing the power conversion efficiency (PCE) and VCR. In addition, the PDL is enhanced by inserting an inductor on the TX board. It reduces the backward-path impedance without increasing the RX volume, boosting the PDL by up to 9.9 times compared to the PDL without the inductor insertion. The proposed IBPT system delivers up to 178.8 $\mu$ W of power at 11.7% of maximum power efficiency with 3.3-V DC output voltage and even 1.385 mW of power with the inductor insertion, supporting various biomedical wearable sensors, such as ECG sensor modules. [ABSTRACT FROM AUTHOR]

This paper presents a PVT-robust error-feedback (EF) noise-shaping SAR (NS-SAR) ADC for direct neural-signal recording. For closed-loop bidirectional neural interfaces enabling the next generation neurological devices, a wide-dynamic-range neural recording circuit is required to accommodate stimulation artifacts. A recording structure using an NS-SAR ADC can be a good candidate because the high resolution and wide dynamic range can be obtained with a low oversampling ratio and power consumption. However, NS-SAR ADCs require an additional gain stage to obtain a well-shaped noise transfer function (NTF), and a dynamic amplifier is often used as the gain stage to minimize power overhead at the cost of vulnerability to PVT variations. To overcome this limitation, the proposed work reutilizes the capacitive-feedback amplifier, which is the analog front-end of the neural recording circuit, as a PVT-robust gain stage to achieve a reliable NS performance. In addition, a new chopper-based implementation of a passive high-pass IIR filter is proposed, achieving an improved NTF compared to prior EF NS-SAR ADCs. Fabricated in a 180-nm CMOS process, the proposed NS-SAR ADC consumes 4.3-μW power and achieves a signal-to-noise-and-distortion ratio (SNDR) of 71.7 dB and 82.7 dB for a bandwidth of 5 kHz and 300 Hz, resulting in a Schreier figure of merit (FOM) of 162.4 dB and 162.1 dB, respectively. Direct neural recording using the proposed NS-SAR ADC is demonstrated successfully in vivo, and also its tolerance against stimulation artifacts is validated in vitro. [ABSTRACT FROM AUTHOR]

This brief reviews the principle and design of dynamic range (DR) enhancement techniques for artifact-tolerant biopotential-acquisition ICs. In order to record small input signals without being disturbed by large artifacts, which may arise from motion or stimulation, biopotential-acquisition ICs for wearable devices and bidirectional neural interfaces should have wide DR in addition to low noise and high power efficiency. This review discusses key features of DR enhancement techniques based on three topologies: (1) saturation-free instrumentation amplifier with analog-to-digital converter (ADC), (2) signal-to-noise-and-distortion ratio (SNDR) enhanced ADC, and (3) DR-enhanced ADC with moderate linearity, which are used in state-of-the-art artifact-tolerant biopotential-acquisition ICs. [ABSTRACT FROM AUTHOR]

A new electrochemical sensor is reported based on a modified platinum (Pt) electrode sequentially drop-casting doped with functionalized multi-walled carbon nanotubes (fMWCNTs) decorated by reduced graphene oxide (rGO) and nickel oxide (NiO) nanoparticles (NPs). The NiO/rGO/fMWCNTs nanohybrid was characterized by Fourier transform infrared spectroscopy (FT-IR), field emission scanning electron microscopy (SEM), X-ray diffraction (XRD), and X-ray fluorescence (XRF). This sensor was employed for the simultaneous determination of catechol and hydroquinone. In the cyclic voltammetry (CV) results for a binary mixture of catechol and hydroquinone, the peak potentials of the two dihydroxybenzene isomers were separated by more than 105 mV, demonstrating the ability of the fabricated sensor to simultaneously determine the analytes. The NiO/rGO/fMWCNTs/Pt electrode exhibited a wide linear range of 10–300 μM with detection limits of 19.86 and 40.18 nM based upon a signal-to-noise ratio of 3 for catechol and hydroquinone, respectively. Furthermore, using differential pulse voltammetry (DPV), the sensor maintained well-defined peaks, demonstrating suitable selectivity. In addition, the NiO/rGO/fMWCNTs/Pt nanocomposite exhibits stability values of 92.3% and 91.6% for catechol and hydroquinone with excellent repeatability. The sensor analyzed water samples with spike recoveries from 90% to 106.66% for catechol and 88% to 98.66% for hydroquinone, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a wireless kitchen fire prevention system that can detect and notify the fire risk caused by gas stoves. The proposed system consists of two modules. The sensor module detects the concentration of carbon dioxide (CO 2 ) near the gas stove and transmits the monitoring results wirelessly. The alarm module, which is placed in other places, receives the data and reminds the user of the stove status. The sensor module uses a cost-efficient electrochemical CO 2 sensor and embeds an in situ algorithm that determines the status of the gas stove based on the measured CO 2 concentration. For the wireless communication between the modules, on-off keying (OOK) is employed, thereby achieving a longer battery lifetime of the alarm module, low cost, and simple implementation. To increase the lifetime further, a wake-up function based on passive infrared (PIR) sensing is employed in the alarm module. Our system can successfully detect the on state of the stove within 40 s and the off state within 200 s. Thanks to the low-power implementation, in situ algorithm, and wake-up function, the alarm module's expected battery lifetime is extended to about two months. [ABSTRACT FROM AUTHOR]

This paper reviews architectures and circuit implementations of on-chip sinusoidal signal generators (SSGs) for electrical impedance spectroscopy (EIS) applications. In recent years, there have been increasing interests in on-chip EIS systems, which measure a target material’s impedance spectrum over a frequency range. The on-chip implementation allows EIS systems to have low power and small form factor, enabling various biomedical applications. One of the key building blocks of on-chip EIS systems is on-chip SSG, which determines the frequency range and the analysis precision of the whole EIS system. On-chip SSGs are generally required to have high linearity, wide frequency range, and high power and area efficiency. They are typically composed of three stages in general: waveform generation, linearity enhancement, and current injection. First, a sinusoidal waveform should be generated in SSGs. The generated waveform’s frequency should be accurately adjustable over a wide range. The firstly generated waveform may not be perfectly linear, including unwanted harmonics. In the following linearity-enhancement step, these harmonics are attenuated by using filters typically. As the linearity of the waveform is improved, the precision of the EIS system gets ensured. Lastly, the filtered voltage waveform is now converted to a current by a current driver. Then, the current sinusoidal signal is injected into the target impedance. This review discusses the principles, advantages, and disadvantages of various techniques applied to each step in state-of-the-art on-chip SSGs. In addition, state-of-the-art designs are compared and summarized. [ABSTRACT FROM AUTHOR]

Herein, a novel catechol sensor made of double-layers of functionalized multi-walled carbon nanotubes coated zinc oxide on a glassy carbon electrode (fMWCNTs/ZnO@fMWCNTs/GCE) is synthesized. The FTIR spectrum reveals that the ZnO NPs are successfully functionalized on the fMWCNT while SEM analysis shows granular colloids on the surface of ZnO@fMWCNTs nanocomposites. The XRD study confirms the crystalline nature of the ZnO peaks and the ZnO interaction with fMWCNTs structure. The fabricated sensor responds to a wide linear range of CC concentrations from 10 µM to 200 µM and sensitivity of 0.0022 µA/µM.cm2 with a detection and quantification limit of 0.027 µM and 0.092 µM, respectively. Both of the limits are better than previously reported ZnO and fMWCNTs sensors. In addition, the developed fMWCNTs/ZnO@fMWCNTs/GCE demonstrates that the electron transfer is regulated by the adsorption-controlled process and can successfully detect catechol in real water samples with an excellent selectivity against hydroquinone (HQ), phenol (ph), and penta-chlorophenol (p-chph). The developed sensor exhibits satisfactory analytical performance including operational stability of 94.5%, good repeatability with a relative standard deviation (RSD) of 2.15%, and reliable reproducibility of 8 electrodes with an RSD of 3.93%. An antifouling double-layered functionalized multi-walled carbon nanotubes (fMWCNTs) coated zinc oxide nanoparticles (ZnO NPs) is synthesized. The nanocomposite (fMWCNTs/ZnO@fMWCNTs) was fabricated using a one-step in-situ adsorption method. In the new design of the fabricated nanocomposite, the diffusion of electrons is improved by the adsorption control mechanism. The developed sensor is highly sensitive and selective for sensing catechol. It exhibits stable and reproducible responses for practical and real analysis of catechol. [ABSTRACT FROM AUTHOR]

This paper presents a frequency-splitting-based wireless power and data transfer IC that simultaneously delivers power and forward data over a single inductive link. For data transmission, frequency-shift keying (FSK) is utilized because the FSK modulation scheme supports continuous wireless power transmission without disruption of the carrier amplitude. Moreover, the link that manifests the frequency-splitting characteristic due to a close distance between coupled coils provides wide bandwidth for data delivery without degrading the quality factors of the coils. It results in large power delivery, high data rate, and high power transfer efficiency. The presented IC fabricated in a 180-nm BCD process simultaneously achieves up-to-115-mW wireless power delivery to the load and 2.5-Mb/s downlink data rate over the single inductive link. The measured overall power efficiency from the DC power supply at the transmitter module to the load at the receiver module reaches 56.7 $\%$ at its maximum, and the bit error rate is lower than 10 $^{-6}$ at 2.5 Mb/s. As a result, the figure of merit (FoM) for data transmission is enhanced by 2 times, and the FoM for power delivery is improved by 38.7 times compared to prior state-of-the-arts using a single inductive link. [ABSTRACT FROM AUTHOR]

In this paper, we present a new impedance measurement integrated circuit (IC) for achieving a wideband coverage up to 10 MHz and low power consumption. A frequency-shift technique is applied to down-shift the input frequency, which ranges from 100 kHz to 10 MHz, into an intermediate frequency of 10 kHz, while the frequency-shifting is bypassed when the input frequency falls in the range from 100 Hz to 100 kHz. It results in 100 times relaxation of the requirement on the instrumentation amplifier (IA) bandwidth and the comparator delay, greatly reducing overall power consumption. The proposed IC employs the polar demodulation structure with a reference resistor that provides reference timing information avoiding any synchronization issue with the transmitter. In order to compensate for the comparator delay and nonlinearity of the IA, the reference magnitude measurement path is added, making only the mismatch of the circuit affects the accuracy. This allows for employing the auto-zeroing technique that can remove the offset but increase the absolute delay by using an additional capacitor to the comparator. The chip fabricated in a 0.18- $\mu$ m CMOS technology consumes the power of 756 $\mu$ W while covering the measurement frequency range from 100 Hz to 10 MHz and exhibiting the maximum magnitude and phase errors of 1.1 $\%$ and 1.9 $^{\circ }$ , respectively. [ABSTRACT FROM AUTHOR]

This brief presents a capacitor-less digital low-dropout (DLDO) regulator, which has low steady-state voltage ripples (VRIPP) and low output noise, suitable for driving analog circuits in system-on-chip devices. To reduce VRIPP, a steady-state control based on ΔΣ modulation and a clock multiplication technique are proposed. Thanks to the ΔΣ operation, the proposed DLDO generates noise-shaped output voltage (VOUT), reducing VRIPP and improving its noise performance without using an output capacitor. The ΔΣ-modulator-based controller is activated just during the steady state, triggered by a lock detector, which continuously tracks VOUT and compares it to a reference VREF. During the steady state, a cyclic time-to-pulse converter and a clock combiner generate an oversampling clock for the controller. The proposed DLDO was fabricated in a 110-nm CMOS process with an active area of 0.07 mm2. The measurement results demonstrate that at VOUT = 0.5 V, VDD = 0.6 V, and ILOAD = 500 μ A, the proposed DLDO achieves < 1 mV of VRIPP, 17.5 dB of power supply rejection (PSR) at 1 MHz, and −151 V2rms/Hz (dB) of power-spectral density at 51.2 kHz. Furthermore, the proposed DLDO achieves 99.77% of current efficiency and 0.25 mV/mA of load regulation while driving the maximum ILOAD of 40 mA. [ABSTRACT FROM AUTHOR]

This article presents an output-capacitorless digital low-dropout regulator (OCL-DLDO) for fine-grained on-chip power delivery and management in system-on-chip devices. The proposed OCL-DLDO incorporates three distinct feedback loops: asynchronous, coarse, and fine loops. The asynchronous loop is activated during drastic load transients, rapidly restoring the output voltage and achieving a small voltage undershoot even without any output capacitor. The coarse loop, which is equipped with adaptive gain adjustment logics based on least-mean-square algorithm, adaptively adjusts the connection of power switches for fast and accurate voltage regulation. Lastly, the fine loop, which is implemented with shift-registers-based control, takes over the control in steady-states for low output voltage ripples and quiescent current. The proposed OCL-DLDO was fabricated in 65 nm CMOS process with an active area of 0.041 mm2. The measurement results show that the proposed OCL-DLDO achieves a peak current efficiency of 99.91% and a figure-of-merit as low as 2.87 fs when driving 25 mA of load current. [ABSTRACT FROM AUTHOR]

A miniaturized, fully integrated wireless power receiver system-on-chip with embedded 16-channel electrode array and data transceiver for electrocortical neural recording and stimulation is presented. An H-tree power and signal distribution network throughout the SoC maintains high quality factor up to 11 in the on-chip receiver coil at 144 MHz resonant frequency while rejecting RF interference in sensitive neural interface circuits owing to its perpendicular and equidistant geometry. A multi-mode buck-boost resonant regulating rectifier (B $^2$ R $^3$) offers greater than 11-dB input dynamic range in RF reception and less than 1 mV overshoot in transient load regulation. At 10 mm link distance, the 9 mm $^2$ neural interface SoC fabricated in a 180 nm silicon-on-insulator (SOI) process attains an overall wireless power transmission system efficiency (WSE) of 3.4% in driving a 160  $\mu$ W load yielding a WSE figure-of-merit of 131, while maintaining signal integrity in analog recording and wireless data transmission that comprise the on-chip load. [ABSTRACT FROM AUTHOR]

Electrochemical impedance spectroscopy (EIS) is a widely used method to characterize the biological materials. In traditional methods for EIS, a sinusoidal current is used to excite the material under test and the measured voltage across that material is demodulated by a linear multiplication with quadrature sinusoidal signals. From the resulting demodulated output, the impedance (magnitude and phase) can be calculated. Although this sine-wave-based impedance measurement method can produce accurate impedance measurements, it requires bulky components and suffers from poor power efficiency due to sinusoidal waveform generation and linear multiplication. Alternatively, a method using square-wave signal, which is simply a clock, for both excitation and demodulation can be much more area and power efficient, but inherently suffers from substantial errors in the result due to significant harmonics in square waves. In this paper, we propose a technique to cancel out the errors caused by such harmonics of the square-wave-based excitation and demodulation. The proposed technique, based on the fact that the magnitude ratio of all the harmonics of a square wave are known, cancels out harmonic errors by subtracting or adding the square-wave-based measured results at higher harmonic frequencies as a simple post-processing calculation. Simulations on specific and also generic impedance models demonstrate the applicability of this technique to various impedance models. Experimental results using a discrete circuit model show that this technique can provide a precise measurement of the impedance with 1% magnitude error and $< $ 0.5° phase error considering just five terms. In addition, measurements with a biological tissue show an average magnitude and phase error of 0.7% and $< \text{0.5}^{\circ }$ , respectively, using the proposed error cancellation. Because this method replaces sinusoidal signal generation and linear multiplication with clock generation and simple switching, it has great potential to be integrated in a wearable and implantable health monitoring device at low area and power consumption. [ABSTRACT FROM AUTHOR]

This paper presents a fully-integrated current-controlled stimulator that is powered directly from on-chip coil antenna and achieves adiabatic energy-replenishing operation without any bulky external components. Adiabatic supply voltages, which can reach a differential range of up to 7.2 V, are directly generated from an on-chip 190-MHz resonant LC tank via a self-cascading/folding rectifier network, bypassing the losses that would otherwise be introduced by the 0.8 V system supply-generating rectifier and regulator. The stimulator occupies 0.22 mm $^2$ in a 180 nm silicon-on-insulator process and produces differential currents up to 145  $\mu$ A. Using a charge replenishing scheme, the stimulator redirects the charges accumulated across the electrodes to the system power supplies for 63.1% of stimulation energy recycling. To benchmark the efficiency of stimulation, a figure of merit termed the stimulator efficiency factor (SEF) is introduced. The adiabatic power rails and energy replenishment scheme enabled our stimulator to achieve an SEF of 6.0. [ABSTRACT FROM AUTHOR]

The parallel combination of a switching and a linear amplifier in the supply modulator for RF power amplifiers (PAs) has the potential to enhance energy efficiency while achieving wider bandwidth and lower ripple output voltage. In this paper, a linear amplifier that features a buffered-switching Class-AB bias scheme is presented for the supply modulator in polar-transmitter structures achieving 500 MHz of small-signal 3-dB bandwidth at a 1.2-V supply. The linear amplifier absorbs and cancels up to 60 mA of ripple current from the switching amplifier. As such, the ripple in the output voltage of the hybrid linear-switching supply modulator is less than 7.5 mVpp. The switching amplifier provides most of the signal current for greatest efficiency owing to a proposed rail-to-rail current-sensing circuit. Current feedback in the switching amplifier achieves 1.68-MHz unity-gain bandwidth at 6-MHz switching frequency. Harmonic distortion in the output voltage of the supply modulator is below 40 dBc at 0.8 Vpp sinusoidal input up to 9 MHz. The peak efficiency is 87.7% for a 8.25- $\Omega $ load, while the maximum output power is 23.6 dBm for a 4.99- $\Omega $ load. The chip measures 1.35 mm2 in a 65-nm standard bulk CMOS process. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated resonant regulating rectifier (IR3) with an on-chip coil used to wirelessly power mm-sized implants. By combining rectification and regulation in a single stage, and controlling this stage via a hybrid pulse-width modulation and pulse-frequency modulation (PFM) feedback scheme, the IR3 avoids efficiency-limiting cascaded losses while enabling tight voltage regulation with low dropout and ripple. The IR3 is implemented in 0.078 mm2 of active area in 180-nm Silicon oxide insulator (SOI) CMOS, and achieves a 1.87% $\Delta V_{{{\textrm{DD}}}}/V_{{{\textrm{DD}}}}$ power supply regulation ratio with a 1-nF decoupling capacitor despite a tenfold load current variation from 8 to 80 $\mu {{\text{A}}}$ . A 0.8-V $V_{{{\textrm{DD}}}}$ is maintained at a 8- ${{\text{k}}}\Omega $ load for 144-MHz RF inputs ranging from 0.98 to 1.5 V. At 1-V regulation, the voltage conversion efficiency is greater than 92% with less than 5.2- ${{\text{m}}}V_{{{\textrm{pp}}}}$ ripple, while the power conversion efficiency is 54%. The measured overall wireless power transfer system efficiency, from the primary coil to $V_{{{\textrm{DD}}}}$ output of the IR3, is 2% at 160- $\mu {{\text{W}}}$ load, and reaches 5% at 700 $\mu {{\text{W}}}$ . [ABSTRACT FROM AUTHOR]

Recent demand and initiatives in brain research have driven significant interest toward developing chronically implantable neural interface systems with high spatiotemporal resolution and spatial coverage extending to the whole brain. Electroencephalography-based systems are noninvasive and cost efficient in monitoring neural activity across the brain, but suffer from fundamental limitations in spatiotemporal resolution. On the other hand, neural spike and local field potential (LFP) monitoring with penetrating electrodes offer higher resolution, but are highly invasive and inadequate for long-term use in humans due to unreliability in long-term data recording and risk for infection and inflammation. Alternatively, electrocorticography (ECoG) promises a minimally invasive, chronically implantable neural interface with resolution and spatial coverage capabilities that, with future technology scaling, may meet the needs of recently proposed brain initiatives. In this paper, we discuss the challenges and state-of-the-art technologies that are enabling next-generation fully implantable high-density ECoG interfaces, including details on electrodes, data acquisition front-ends, stimulation drivers, and circuits and antennas for wireless communications and power delivery. Along with state-of-the-art implantable ECoG interface systems, we introduce a modular ECoG system concept based on a fully encapsulated neural interfacing acquisition chip (ENIAC). Multiple ENIACs can be placed across the cortical surface, enabling dense coverage over wide area with high spatiotemporal resolution. The circuit and system level details of ENIAC are presented, along with measurement results. [ABSTRACT FROM AUTHOR]

We present a telemetry IC with a new data modulation scheme for efficient simultaneous transfer of power and backward data over a single inductive link. Data-driven synchronized single-cycle shorting of the secondary LC tank conserves reactive energy while inducing an instantaneous voltage change on the primary side. Contrary to conventional load shift keying modulation, the recovery time of the secondary LC oscillation after shorting improves asymptotically with increasing quality factor of the secondary LC tank. Since quality factor does not reduce the data rate, the LC tank can be simultaneously optimized for power and data telemetry, obviating the conventional tradeoff between power transfer efficiency and data rate. Cyclic ON-OFF keying time-encoded symbol data mapping of the shorting cycle allows transmission of two data bits per four carrier cycles while supporting simultaneous power delivery during at least six nonshorting out of eight half cycles. All timing control signals for rectification and data transmission are generated from a low-power clock recovery comparator and a phased-locked loop. The 0.92 mm2 65 nm CMOS IC delivers up to 11.5 mW power to the load and simultaneously transmits 6.78 Mb/s data while dissipating 64 \mu \textW power. A bit error rate of ≤9.9 \times 10^-8 was measured over a single 1 cm 13.56 MHz inductive link at a data rate of 6.78 Mb/s with a 10 mW load power. [ABSTRACT FROM PUBLISHER]

A four-channel multi-input multi-output (MIMO) complex baseband receiver for spectrum and space-aware cognitive radio applications is presented. The MIMO baseband receiver comprises a capacitive harmonic-rejection downconverting mixer (HRM) receiver and a signal-separation multi-input multi-output analog core (MAC) on a single integrated circuit. The HRM receiver performs frequency selection of the incoming RF signals by programmable spectral downconversion and filtering with minimal harmonic folding. The subsequent MAC separates the spectrally overlapping but spatially diverse signals by weighted complex matrix multiplication. The entire signal path is implemented using energy-efficient $g_m$-C$ analog circuits with digitally controlled capacitive weighting for configurable baseband down-/upconversion ranging from -$24 to +$24 MHz in the HRM, and programmable spatial filtering with 4\times$4 complex (8 active area, and consumes 480 $\upmu$W digital power at 45 MHz LO and 840 $\upmu$W analog power at 3 MHz baseband from a 1.2 V supply. [ABSTRACT FROM PUBLISHER]

This paper presents an overview of the fundamentals and state of the-art in noninvasive physiological monitoring instrumentation with a focus on electrode and optrode interfaces to the body, and micropower-integrated circuit design for unobtrusive wearable applications. Since the electrode/optrode–body interface is a performance limiting factor in noninvasive monitoring systems, practical interface configurations are offered for biopotential acquisition, electrode–tissue impedance measurement, and optical biosignal sensing. A systematic approach to instrumentation amplifier (IA) design using CMOS transistors operating in weak inversion is shown to offer high energy and noise efficiency. Practical methodologies to obviate 1/f noise, counteract electrode offset drift, improve common-mode rejection ratio, and obtain subhertz high-pass cutoff are illustrated with a survey of the state-of-the-art IAs. Furthermore, fundamental principles and state-of-the-art technologies for electrode–tissue impedance measurement, photoplethysmography, functional near-infrared spectroscopy, and signal coding and quantization are reviewed, with additional guidelines for overall power management including wireless transmission. Examples are presented of practical dry-contact and noncontact cardiac, respiratory, muscle and brain monitoring systems, and their clinical applications. [ABSTRACT FROM PUBLISHER]

This paper presents an error-tolerant and power-efficient impedance measurement scheme for bioimpedance acquisition. The proposed architecture measures the magnitude and the real part of the target complex impedance, unlike other impedance measurement architectures measuring either the real/imaginary components or the magnitude and phase. The phase information of the target impedance is obtained by using the ratio between the magnitude and the real components. This can allow for avoiding direct phase measurements, which require fast, power-hungry circuit blocks. A reference resistor is connected in series with the target impedance to compensate for the errors caused by the delay in the sinusoidal signal generator and the amplifier at the front. Moreover, an additional magnitude measurement path is connected to the reference resistor to cancel out the nonlinearity of the proposed system and enhance the settling speed of the low-pass filter by a ratio-based detection. Thanks to this ratio-based detection, the accuracy is enhanced by 30%, and the settling time is improved by 87.7% compared to the conventional single-path detection. The proposed integrated circuit consumes only 513 μ W for a wide frequency range of 10 Hz to 1 MHz, with the maximum magnitude and phase errors of 0.3% and 2.1 ° , respectively. [ABSTRACT FROM AUTHOR]

Cardiovascular diseases (CVDs) have been listed among the most deadly diseases worldwide. Many CVDs are likely to manifest their symptoms some time prior to the onset of any adverse or catastrophic events, and early detection of cardiac abnormalities is incredibly important. However, traditional electrocardiography (ECG) monitoring systems face challenges with respect to their scalability and affordability as they require direct body contact and cumbersome equipment. As a step forward from the large-scale direct-contact ECG monitoring devices, which are inconvenient for the user in terms of wearability and portability, in this research, we present a small-sized, non-contact, real-time recording system for mobile long-term monitoring of ECG signals. The device mainly comprises three non-contact electrodes to sense the bio-potential signal, an AD8233 AFE IC to extract the ECG signal, and a CC2650 MCU to read, filter, and transmit them. The device is powered by a 2000 mAh lithium-ion battery with isolation between digital and analog powers on the board using two low-dropout regulators (LDOs). The board's dimension is 8.56 cm × 5.4 cm, the size of a credit card, making it optimal to be worn in a shirt chest pocket. In spite of its small form factor, the device still manages to achieve a continuous measurement battery life of over 16 h, total harmonic distortion below −30 dB across the interested frequency range, an input-referred noise as low as 1.46 µV for contacted cases and 5.15 µV for non-contact cases through cotton, and clear ECG recording for both contact and non-contact sensing, all at a cost around USD 50. [ABSTRACT FROM AUTHOR]

Wireless power transmission (WPT) using an inductively coupled link is one of the most popular approaches to deliver power wirelessly to biomedical implants. As the electromagnetic wave travels through the tissue, it is attenuated and absorbed by the tissue, resulting in much weaker electromagnetic coupling than in the air. As a result, the received input power on the implant is very weak, and so is the input voltage at the rectifier, which is the first block that receives the power on the implant. With such a small voltage amplitude, the rectifier inevitably has a very poor power conversion efficiency (PCE), leading to a poor power transfer efficiency (PTE) of the overall WPT system. To address this challenge, we propose a new system-level WPT method based on duty cycling of the power transmission for millimeter-scale implants. In the proposed method, the power transmitter (TX) transmits the wave with a duty cycle. It transmits only during a short period of time and pauses for a while instead of transmitting the wave continuously. In doing so, the TX power during the active period can be increased while preserving the average TX power and the specific absorption rate (SAR). Then, the incoming voltage becomes significantly larger at the rectifier, so the rectifier can rectify the input with a higher PCE, leading to improved PTE. To investigate the design challenges and applicability of the proposed duty-cycled WPT method, a case for powering a 1 × 1-mm 2 -sized neural implant through the skull is constructed. The implant, a TX, and the associated environment are modeled in High-Frequency Structure Simulator (HFSS), and the circuit simulations are conducted in Cadence with circuit components in a 180-nm CMOS process. At a load resistor of 100 k Ω , an output capacitor of 4 nF, and a carrier frequency of 144 MHz, the rectifier's DC output voltage and PCE are increased by 300% (from 1.5 V to 6 V) and by 50% (from 14% to 64%), respectively, when the duty cycle ratio of the proposed duty-cycled power transmission is varied from 100% to 5%. [ABSTRACT FROM AUTHOR]