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In past years, LLC resonant converters have become a mainstream topology for dc–dc power conversion due to their advantages, such as the superior efficiency obtained with the soft switching of MOSFETs. In order to further improve the efficiency of the converter, synchronous rectification (SR) can be implemented as an alternative for diode rectification. As a result, the vast majority of the literature related to this field of study presents different LLC SR control algorithms, which aim to improve the operation of the rectification. Unlike prior work on SR controllers, this paper contributes to the area of power loss estimation using rectifier current equations (RCE). The developed method based on time-domain analysis of SR currents provides a new analytical framework to characterize the behavior of SR. Implications in SR power losses of different time delays are investigated using the developed loss estimation method. In addition, different converter design parameters, such as choice of inductance ratio, can be analyzed. The RCE captures the true discontinuous and complex behavior of SR, which is often oversimplified by the conventional first-harmonic approximation (FHA). As a result, the proposed method facilitates the design of LLC resonant converters and provides increased precision in SR power loss estimation when compared to FHA, and in a considerably faster fashion when compared with precise yet computationally intensive simulation software. This paper is validated with simulation and experimental results. [ABSTRACT FROM AUTHOR]

In the past ten years, LLC resonant converters have become a mainstream topology for dc/dc power conversion, and multiple design tools have been developed for this topology, including controllers, regulators, soft-switching techniques, etc. While many tools are available for designing this converter, techniques for accurately determining power losses in the inverter mosfets of the topology based on time-domain analysis have not been fully explored yet. Precise power loss estimation is fundamental to determine the thermal behavior of the switches before the converter is built, which accelerates and optimizes the thermal management design process. In addition, accurate methods of estimating conduction losses, which are dominant in this topology, switching losses, and body diode losses are lacking in the literature. This paper proposes a method for enhancing power loss estimation in LLC inverter mosfets based on time-domain analysis of the converter. Moreover, a detailed characterization of mosfet's conduction losses ($P_{\text{cond}}$), switching losses ($P_{\text{sw}}$), and body diode losses ($P_{\text{diode}}$), including the effects of different parameters such as gate-source voltage ($V_{\text{GS}}$), junction temperature ($T_{j}$), drain current ($\displaystyle I_{D}$), and drain-source voltage ($V_{\text{DS}}$), is presented, which can further improve power loss assessment in this topology. The developed method based on time interval analysis replaces the simplistic first-harmonic approximation (FHA), which allows for improved power loss calculations. Further improvement is obtained with the detailed characterization of the switching device. As verified by simulation and experimental results, the proposed estimation tool provides a significant boost in accuracy for power loss determination when compared to the existing method for power loss estimation using FHA. [ABSTRACT FROM AUTHOR]