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Background: Art therapy has a long history of applications in cognitive and motor rehabilitation. More recently, a growing body of scientific literature has highlighted the potential of virtual reality in neurorehabilitation, though it has focused more on the technology itself than on the principles adopted in digital scenarios. Methods: This study is a single-blind randomized controlled trial conducted on 40 patients with stroke, comparing conventional therapy (physical therapy for the upper and lower limbs, for posture and balance, cognitive therapy, occupational therapy, speech therapy, and specific therapy for swallowing, bowel, and bladder dysfunctions) to a protocol in which the upper limb physical therapy was substituted with art therapy administered by means of virtual reality exploiting the so-called Michelangelo effect. Results: After 12 sessions, patients in the virtual art therapy group showed a significantly greater improvement in independence in activities of daily living, as assessed by the Barthel Index (interaction of time and group: p = 0.001). Significant differences were also found in terms of upper limb muscle strength (Manual Muscle Test, p < 0.01) and reduction in spasticity (Ashworth scale, p = 0.007) in favor of the experimental group. In the virtual art therapy group, the effectiveness of the intervention was significantly correlated with patient participation (Pittsburgh Rehabilitation Participation Scale: R = 0.41), patient satisfaction (R = 0.60), and the perceived utility of the intervention by the therapist (R = 0.43). Conclusions: These findings support the efficacy of virtual art therapy leveraging the Michelangelo effect. Further studies should also focus on cognitive domains that could benefit from this type of approach. [ABSTRACT FROM AUTHOR]

Processing large-scale graphs is challenging due to the nature of the computation that causes irregular memory access patterns. Managing such irregular accesses may cause significant performance degradation on both CPUs and GPUs. Thus, recent research trends propose graph processing acceleration with Field-Programmable Gate Arrays (FPGA). FPGAs are programmable hardware devices that can be fully customised to perform specific tasks in a highly parallel and efficient manner. However, FPGAs have a limited amount of on-chip memory that cannot fit the entire graph. Due to the limited device memory size, data needs to be repeatedly transferred to and from the FPGA on-chip memory, which makes data transfer time dominate over the computation time. A possible way to overcome the FPGA accelerators' resource limitation is to engage a multi-FPGA distributed architecture and use an efficient partitioning scheme. Such a scheme aims to increase data locality and minimise communication between different partitions. This work proposes an FPGA processing engine that overlaps, hides and customises all data transfers so that the FPGA accelerator is fully utilised. This engine is integrated into a framework for using FPGA clusters and is able to use an offline partitioning method to facilitate the distribution of large-scale graphs. The proposed framework uses Hadoop at a higher level to map a graph to the underlying hardware platform. The higher layer of computation is responsible for gathering the blocks of data that have been pre-processed and stored on the host's file system and distribute to a lower layer of computation made of FPGAs. We show how graph partitioning combined with an FPGA architecture will lead to high performance, even when the graph has Millions of vertices and Billions of edges. In the case of the PageRank algorithm, widely used for ranking the importance of nodes in a graph, compared to state-of-the-art CPU and GPU solutions, our implementation is the fastest, achieving a speedup of 13 compared to 8 and 3 respectively. Moreover, in the case of the large-scale graphs, the GPU solution fails due to memory limitations while the CPU solution achieves a speedup of 12 compared to the 26x achieved by our FPGA solution. Other state-of-the-art FPGA solutions are 28 times slower than our proposed solution. When the size of a graph limits the performance of a single FPGA device, our performance model shows that using multi-FPGAs in a distributed system can further improve the performance by about 12x. This highlights our implementation efficiency for large datasets not fitting in the on-chip memory of a hardware device. [ABSTRACT FROM AUTHOR]

In neurorehabilitation, some studies reported the effective use of art therapy for reducing psychological disorders and for enhancing physical functions and cognitive abilities. Neuroaesthetical studies showed that seeing an art masterpiece can spontaneously elicit a widespread brain arousal, also involving motor networks. To combine contemplative and performative benefits of art therapy protocols, we have developed an immersive virtual reality system, giving subjects the illusion that they are able to paint a copy of famous artistic paintings. We previously observed that during this virtual task, subjects perceived less fatigue and performed more accurate movements than when they were asked to color the virtual canvas. We named this upshot the Michelangelo effect. The aim of this study was to test the rehabilitative efficacy of our system. Ten patients with stroke in the subacute phase were enrolled and trained for one month with virtual art therapy (VAT) and physiotherapy. Their data were compared with those of ten patients matched for pathology, age and clinical parameters, trained only with conventional therapy for the same amount of time. The VAT group showed a significantly higher improvements in the Barthel Index score, a measure of independency in activities of daily living (66 ± 33% vs. 31 ± 28%, p = 0.021), and in pinching strength (66 ± 39% vs. 18 ± 33%, p = 0.008), with respect to the group treated with conventional rehabilitation. [ABSTRACT FROM AUTHOR]

Byline: Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete In this work, it is shown how a DBMS workload, running on a shared-bus shared-memory multiprocessor, can be accelerated by adding simple support to the MESI coherence protocol. As a DBMS workload, we choose the TPC-D benchmark running on the PostgreSQL DBMS. Results show that, for a DSS workload, the use of a WU protocol with a selective invalidation strategy for private data improves performance because of the access pattern to shared data and the lower bus utilisation due to the absence of invalidation miss, when the contribution of passive sharing is eliminated. In the 16 processor case, the advantage can be quantified in a 20% of increased performance. Finally, it is shown how results can be extended to other DBMS workloads.

Translating a system requirement into a low-level representation (e.g., register transfer level or RTL) is the typical goal of the design of FPGA-based systems. However, the Design Space Exploration (DSE) needed to identify the final architecture may be time consuming, even when using high-level synthesis (HLS) tools. In this article, we illustrate our hybrid methodology, which uses a frontend for HLS so that the DSE is performed more rapidly by using a higher level abstraction, but without losing accuracy, thanks to the HP-Labs COTSon simulation infrastructure in combination with our DSE tools (MYDSE tools). In particular, this proposed methodology proved useful to achieve an appropriate design of a whole system in a shorter time than trying to design everything directly in HLS. Our motivating problem was to deploy a novel execution model called data-flow threads (DF-Threads) running on yet-to-be-designed hardware. For that goal, directly using the HLS was too premature in the design cycle. Therefore, a key point of our methodology consists in defining the first prototype in our simulation framework and gradually migrating the design into the Xilinx HLS after validating the key performance metrics of our novel system in the simulator. To explain this workflow, we first use a simple driving example consisting in the modelling of a two-way associative cache. Then, we explain how we generalized this methodology and describe the types of results that we were able to analyze in the AXIOM project, which helped us reduce the development time from months/weeks to days/hours. [ABSTRACT FROM AUTHOR]

Objective. Following current model of body representations, we aimed to systematically investigate the association between brain modifications, in terms of grey matter loss, and body representation deficits, in terms of alterations of the body schema (BS) and of non-action oriented body representations (NA), in individuals with lower limb amputation (LLA). Method. BS and NA (both semantic and visuospatial NA) were evaluated in 11 healthy controls and in 14 LLA, considering the impact of clinical variables such as prosthesis use. The association between BS and NA deficits and grey matter loss was also explored in LLA by using Voxel Based Morphometry analysis. Results. LLA's performance was fine in terms of semantic NA, while it showed behavioural impairments both in BS and visuospatial NA as compared to healthy controls. Interestingly the visuospatial NA performance was related to the amount of prosthesis use. NA deficits in terms of visuospatial body map processing were associated with grey matter reduction in left (lobule VIII) and right (crus II) cerebellum, while BS deficits were associated with grey matter reduction in right anterior cingulate cortex and the bilateral cuneus. No significant association was detected for semantic NA. Conclusion. The study of BS and NA representations after limb loss has informed our understanding of the different dynamics (i.e., adjustments to body change) of such representations, supporting current cognitive models of body representation. The clinical relevance of present findings is also discussed. [ABSTRACT FROM AUTHOR]

Passive Shared Copy Removal (PSCR) is presented as a simple coherence protocol that is capable of eliminating the occurrence of passive sharing by using data from the compiler that is usually available in operating system kernels. PSCR, which has been tested against other passive sharing solutions by enhanced trace-driven simulation, is also capable of limiting the coherence-maintaining overhead by utilizing data regarding access patterns to shared information that are also present in parallel applications.

The main goal of the AXIOM project is to design a small board that could be used as a LEGO™-style module to build systems with more performance while keeping the programming task simple by using a familiar sharedmemory programming model. The interconnection plays a crucial role both for the need of providing fast and reliable communication (including lossless control flow as, e.g., Infiniband, but with a simplified scope and cost). In this paper, we outline some of our initial choices and explore the performance of RDMA based mechanisms and interfaces, including the remote memory management behind the programming model. Our initial results show a potential for scaling the system as we use DF-Threads, good bandwidth for RDMA transfers, promising to scale once we use the OmpSs, programming model. [ABSTRACT FROM AUTHOR]

We present a new type of soft-core processor called the “Data-Flow Soft-Core” that can be implemented through FPGA technology with adequate interconnect resources. This processor provides data processing based on data-flow instructions rather than control flow instructions. As a result, during an execution on the accelerator of the Data-Flow Soft-Core, both partial data and instructions are eliminated as traffic for load and store activities. Data-flow instructions serve to describe a program and to dynamically change the context of a data-flow program graph inside the accelerator, on-the-fly. Our proposed design aims at combining the performance of a fine-grained data-flow architecture with the flexibility of reconfiguration, without requiring a partial reconfiguration or new bit-stream for reprogramming it. The potential of the data-flow implementation of a function or functional program can be exploited simply by relying on its description through the data-flow instructions that reprogram the Data-Flow Soft-Core. Moreover, the data streaming process will mirror those present in other FPGA applications. Finally, we show the advantages of this approach by presenting two test cases and providing the quantitative and numerical results of our evaluations. [ABSTRACT FROM AUTHOR]

In specific domains, such as cyber-physical systems, platforms are quickly evolving to include multiple (many-) cores and programmable logic in a single system-on-chip, while including interfaces to commodity sensors/actuators. Programmable Logic (e.g., FPGA) allows for greater flexibility and dependability. However, the task of extracting the performance/watt potential of heterogeneous many-cores is often demanded at the application level, and this has strong implication on the HW/SW co-design process. Enabling fast prototyping of a board being designed is paramount to enable low time-to-market for applications running on it, and ultimately, for the whole platform: programmers must be provided with accurate hardware models, to support the software development cycle at the very early stages of the design process. Virtual platforms fulfill this need, providing that they can be in turn efficiently developed and tested in a few months timespan. In this position paper we will share our experience in the sphere of the AXIOM project, identifying key properties that virtual platforms modeling next-generation cyber-physical systems should have to quickly enable simulation-based software development for a these platforms. [ABSTRACT FROM AUTHOR]

In specific domains, such as cyber-physical systems, platforms are quickly evolving to include multiple (many-) cores and programmable logic in a single system-on-chip, while including interfaces to commodity sensors/actuators. Programmable Logic (e.g., FPGA) allows for greater flexibility and dependability. However, the task of extracting the performance/watt potential of heterogeneous many-cores is often demanded at the application level, and this has strong implication on the HW/SW co-design process. Enabling fast prototyping of a board being designed is paramount to enable low time-to-market for applications running on it, and ultimately, for the whole platform: programmers must be provided with accurate hardware models, to support the software development cycle at the very early stages of the design process. Virtual platforms fulfill this need, providing that they can be in turn efficiently developed and tested in a few months timespan. In this position paper we will share our experience in the sphere of the AXIOM project, identifying key properties that virtual platforms modeling next-generation cyber-physical systems should have to quickly enable simulation-based software development for a these platforms. [ABSTRACT FROM AUTHOR]

Elliptic-Curve cryptography (ECC) is promising for enabling information security in constrained embedded devices. In order to be efficient on a target architecture, ECCs require accurate choice/tuning of the algorithms that perform the underlying mathematical operations. This paper contributes with a cycle-level analysis of the dependencies of ECC performance from the interaction between the features of the mathematical algorithms and the actual architectural and microarchitectural features of an ARM- based Intel XScale processor. Another contribution is the cycle-level analysis of a modified ARM processor that includes a word- level finite field polynomial multiplier (poly_mul) in its data path. This extension constitutes a good trade-off between applicability in a number of contexts, the simplicity of integration within the processor, and performance. This paper points out the most advantageous mix of elliptic curve (EC) parameters both for the standard ARM-based Intel XScale platform and for the one equipped with the poly_mul unit. In particular, the latter case allows for more than 41 percent execution time reduction on the considered benchmarks. Last, this paper investigates the correlation between the possible architectural organizations of a processor equipped with poly_mul unit(s) and EC benchmark performance. For instance, only superscalar pipelines can exploit the features of out-of-order execution and only very complex organizations (for example, four way superscalar) can exploit a high number of available ALUs. Conversely, we show that there are no benefits in endowing the processor with more than one poly_mul, and we point out a possible trade-off between performance and complexity increase: A two-way in-order/out-of-order pipeline allows +50 percent and +90 percent of Instructions per Cycle (IPC), respectively. Finally, we show that there are no critical constraints on the latency and pipelining capability of the poly_mul unit for the basic EC point multiplication. [ABSTRACT FROM AUTHOR]

Abstract: In this work, we characterized the memory performance—and in particular the impact of coherence overhead and process migration—of a shared-bus shared-memory multiprocessor running a DSS workload. When the number of processors is increased in order to achieve higher computational power, the bus becomes a major bottleneck of such architecture. We evaluated solutions that can greatly reduce that bottleneck. An area where this kind of optimization is important regards data base systems. For this reason, we considered a DSS workload and we setup the experiments following TPC-D specifications on the PostgreSQL DBMS in order to explore different optimizations on same kind of workloads as evaluated in the literature. In this scenario, we compare possible solutions to boost performance and we show the impact of process migration on coherence overhead. We found that the consequences of coherence overhead and process migration on performance are very important in machines with 16 or more processors. In this case, even little sharing, as in DSS applications, can become crucial for system performance. Another important result of our analysis regards the interaction between the coherence protocol and the scheduler. The basic cache affinity scheduling is useful in reducing migration, but it is not effective in every load condition. Specific coherence protocols can help reduce the effects of process migration, especially in situations when the scheduler cannot apply the affinity requirement. In these conditions, the use of a write-update protocol with a selective invalidation strategy for private data improves performance (and scalability) of about 20% with respect to a classical MESI-based solution. This advantage is about 50% in the case of high cache-to-cache transfer. [Copyright &y& Elsevier]

The article discusses several issues on the use of embedded single-chip multicore architectures. Problems occur in terms of wire-delay, design complexity and power requirements. Many researchers have started to look at building multiprocessors on a single chip, following both past and novel design solutions. Cache and memory subsystems are important in order to develop future embedded single-chip multicore architectures.

El artículo discurre sobre la cantidad de basura producida en Europa y el fenómeno conocido como la mina urbana, o la búsqueda de cosas valiosas en la basura. El autor comenta sobre las políticas gubernamentales asociadas con el tratamiento de la basura. También se considera la implementación de sistemas de reciclaje por la región.

Elliptic-Curve cryptography (ECC) is promising for enabling information security in constrained embedded devices. In order to be efficient on a target architecture, ECCs require accurate choice/tuning of the algorithms that perform the underlying mathematical operations. This paper contributes with a cycle-level analysis of the dependencies of ECC performance from the interaction between the features of the mathematical algorithms and the actual architectural and microarchitectural features of an ARM- based Intel XScale processor. Another contribution is the cycle-level analysis of a modified ARM processor that includes a word- level finite field polynomial multiplier (poly_mul) in its data path. This extension constitutes a good trade-off between applicability in a number of contexts, the simplicity of integration within the processor, and performance. This paper points out the most advantageous mix of elliptic curve (EC) parameters both for the standard ARM-based Intel XScale platform and for the one equipped with the poly_mul unit. In particular, the latter case allows for more than 41 percent execution time reduction on the considered benchmarks. Last, this paper investigates the correlation between the possible architectural organizations of a processor equipped with poly_mul unit(s) and EC benchmark performance. For instance, only superscalar pipelines can exploit the features of out-of-order execution and only very complex organizations (for example, four way superscalar) can exploit a high number of available ALUs. Conversely, we show that there are no benefits in endowing the processor with more than one poly_mul, and we point out a possible trade-off between performance and complexity increase: A two-way in-order/out-of-order pipeline allows +50 percent and +90 percent of Instructions per Cycle (IPC), respectively. Finally, we show that there are no critical constraints on the latency and pipelining capability of the poly_mul unit for the basic EC point multiplication. [ABSTRACT FROM AUTHOR]