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As the power required by modern data center processors increases, the power architecture must be adapted; for example, 48 V distribution voltage allows to reduce copper losses by a factor 16 with respect to the use of traditional 12 V power architecture. In order to generate the required processor core voltage, a two-stage approach is usually preferred, where the intermediate bus voltage is generated using an unregulated resonant dc–dc converter as, for instance, an LLC converter. Compared to LLCs, hybrid resonant switched-capacitor converters (ReSCCs) make it possible to achieve large voltage conversion ratios without the need of high turns ratio transformers. In this letter, a novel hybrid ReSCC that performs a 48–3.4 V direct conversion is presented. A prototype of the proposed converter has been implemented, capable of providing a continuous output power of 440 W with a maximum efficiency of 96.3% at 30 A load current. [ABSTRACT FROM AUTHOR]

Inductor current sensing is becoming widely used in current programmed controllers for microprocessor applications. This method exploits a low-pass filter in parallel with the inductor to provide lossless current sense. A major drawback of inductor current sensing is that accurate sense the dc and ac components of the current signal requires precise matching between the low-pass filter time constant and the inductor time constant (L/[R.sub.L]). However, matching accuracy depends on the tolerance of the components and on the operating conditions; therefore it can hardly be guaranteed. To overcome this problem, a novel digital autotuning system is proposed that automatically compensates any time constant mismatch. This autotuning system has been developed for voltage regulator module (VRM) current programmed controllers. It makes it possible to meet the adaptive voltage positioning requirements using conventional and low cost components, and to solve problems such as aging effects, temperature variations, and process tolerances as well. A prototype of the autotuning system based on a field-programmable gate array and a commercial dc/dc controller has been designed and tested. The experimental results fully confirmed the effectiveness of the proposed method, showing an improvement of the current sense precision from about 30 % up to 4%. This innovative solution is suitable to fulfill the challenging accuracy specifications required by the future VRM applications. Index Terms--Current mode control, inductor current sensing techniques, VRM.

This paper investigates a mixed-signal fixed frequency digital voltage-mode controller for dc-dc converters. Switch turn-on is determined by system clock, while switch turn-off is determined asynchronously by comparing a signal proportional to the derivative of the output voltage and the voltage ramp driven by the digital-to-analog converter (DAC). One of the most important features is that the derivative action of the proportional-integral-derivative (PID) voltage-mode controller is inherently obtained by a combination of the analog front-end and the hard-wired digital logic, without requiring the numerical computation of the derivative action nor analog reactive elements (capacitors), which are usually needed for the derivative action in the analog domain and which are critical for the IC controller integration. Moreover, as compared to conventional digital approaches based on analog-to-digital converters (ADCs) and digital pulsewidth modulators (DPWMs), the phase-lag due to the uniformly sampled DPWM and due to the output voltage sampling is avoided, thus improving phased margin at the crossover frequency where the derivative contribution is usually prevailing. This property potentially enables faster controllers with improved dynamic response, breaking bandwidth limitation of conventional digital control architectures. The proposed control architecture is also effective from the IC point of view, since it is based on a DAC, a simple analog front-end, including a sample and hold, a comparator and an operational amplifier, and low digital signal-processing requirement (~5000 gates). Simulation and experimental results on a 1.2 V-20 A synchronous buck converter confirm the properties of the proposed solution. Index Terms--DC-DC converters, mixed-signal control, point-of-load converters, voltage-mode control.

This paper investigates a mixed synchronous/asynchronous digital voltage-mode controller for DC-DC converters. In the proposed control architecture, the turn-on switching event is determined asynchronously by comparing the converter output voltage and a synchronously generated voltage ramp driven by the digital control using a low-resolution digital-to-analog converter. Switch turn-off is determined synchronously by the system clock. In the proposed approach, the derivative action of the proportional-integral-derivative voltage-mode controller is inherently obtained by the frequency modulation, without requiring the digital computation of the derivative action. A simplified small-signal model is also derived in order to analyze the performance achievable by the proposed solution. This control architecture features good dynamic performance, and frequency modulation during transients. Simulation and experimental results on a synchronous buck converter, where the digital control has been implemented in field programmable gate array, confirm the effectiveness of the proposed solution. Index Terms--Digital control, DC-DC converters, mixed-signal control, voltage-mode control.

This paper proposes a simple autotuning technique for digitally controlled dc-dc converters. The proposed approach is based on the relay feedback method and introduces perturbations on the output voltage during converter soft-start. By using an iterative procedure, the tuning of proportional-integral-derivative parameters is obtained directly by including the controller in the relay feedback and by adjusting the controller parameters based on the specified phase margin and control loop bandwidth. A nice property of the proposed solution is that output voltage perturbations are introduced while maintaining the relay feedback control on the output voltage. The proposed algorithm is simple, requires small tuning times, and it is compliant with the cost/complexity constraints of integrated digital integrated circuits. Simulation and experimental results of a synchronous buck converter and of a dc-dc boost converter confirm the effectiveness of the proposed solution. Index Terms--Controller autotuning, dc-dc converters, digital control.

This paper describes an innovative digital control architecture for low-voltage, high-current dc-dc converters, based on a combination of current-programmed control and variable frequency operation. The key feature of the proposed architecture is the low complexity: only two digital-to-analog converters (DACs) with low resolution (7-b) are used for control. An original control algorithm is used to reduce quantization effects to negligible levels, in spite of the low resolution of the DACs. Thanks to this algorithm, both static and dynamic output voltage regulation are improved with respect to traditional digital solutions. Adaptive voltage positioning and active current sharing are inherently provided by the new architecture. A detailed description of the control strategy is given with reference to a single-phase buck converter. Extension to multiphase converters is straightforward. The digital control architecture is experimentally verified on a FPGA-based four-phase prototype buck converter operating at 350 kHz/phase. Output voltage tolerance within [+ or -] 0.5 % is experimentally demonstrated, along with negligible quantization effects and fast transient response. The features and the performance of the proposed architecture make it a valuable candidate for the control of next generation voltage regulator modules. Index Terms--Current-programmed control, dc-dc switching power converters, digital control.

A single photon avalanche detector (SPAD) in planar technology is described and discussd.

At the present time, Single Photon Avalanche Diodes (SPADs) are the enabling devices in many applications, ranging from medical imaging to laser ranging and from remote sensing to quantum key distribution. Even though they belong to different scientific domains, these applications share the need for a detector capable of attaining high count rates possibly without trading it off with other key detector's features, such as afterpulsing probability, photon detection efficiency, and dark counts. In this work, we present the characterization of a fast integrated active quenching circuit capable of driving high-performance external custom-technology SPADs for single photon detection in the visible wavelength range. Combining the prompt intervention of the electronic circuitry and the performance of a custom-technology SPAD, we attained count rates up to 250 MCps while keeping the afterpulsing probability within 2%. [ABSTRACT FROM AUTHOR]

Design and testing of a monolithic integrated dual-detector for photon correlation analysis is described. The main element is a single photon avalanche diode (SPAD) with low noise- and high time-resolution.

A process probe, able to measure the avalanche ignition rate of generation centers, is proposed for use in p-n junctions.

A single-photon avalanche diode detector is presented. This avalanche detector was specifically developed to produce a time response not influenced by tail effects and secondary bumps, which is achieved through the instrument's capacity for picosecond time-correlated single photon counting. Evaluation of its performance show that it produces an instrument response function with ultraclean shape and steep decay.

A high-speed silicon photodetector, compatible with very-large-scale integration technologies, is suitable for fabricating monolithic receivers for optical data link applications. The detector operates in the low-voltage range at wavelengths of 780-850 nanometers. The photodetector contains an interdigitated p-i-n detector grown on a silicon-on-insulator substrate. The fabricated devices show low dark currents, large dynamic range and small capacitance.

Photonic quantum technologies promise a revolution of the world of information processing, from simulation and computing to communication and sensing, thanks to the many advantages of exploiting single photons as quantum information carriers. In this scenario, single‐photon detectors play a key role. On the one hand, superconducting nanowire single‐photon detectors (SNSPDs) are able to provide remarkable performance on a broad spectral range, but their applicability is often limited by the need of cryogenic operating temperatures. On the other hand, single‐photon avalanche diodes (SPADs) overcome the intrinsic limitations of SNSPDs by providing a valid alternative at room temperature or slightly below. In this paper, the authors review the fundamental principles of the SPAD operation and provide a thorough discussion of the recent progress made in this field, comparing the performance of these devices with the requirements of the quantum photonics applications. In the end, the authors conclude with their vision of the future by summarizing prospects and unbeaten paths that can open new perspectives in the field of photonic quantum information processing. [ABSTRACT FROM AUTHOR]

In this letter, we present the timing performance of an optimized red-enhanced single-photon avalanche diode (RE-SPAD) manufactured with a fully custom fabrication process. The detector has been characterized with an external CMOS front end circuit able to read out the RE-SPAD avalanche current and provide the timing information with state-of-the-art jitter. In particular, the careful minimization of the RE-SPAD capacitive parasitics, along with the transimpedance architecture and the gigahertz bandwidth of the front end circuit, allowed the achievement of a timing jitter as low as 83 ps full width at half maximum that increases only up to 103 ps for a detection threshold as high as 600 mV. This feature makes it possible to implement high-threshold detection systems insensitive to the electrical disturbances coming from other SPADs integrated in the same chip, demonstrating that the extension of this work to multichannel systems is feasible. [ABSTRACT FROM AUTHOR]

In this letter, the development and the experimental characterization of a new photon detection module, based on a 32 × 1 red-enhanced single-photon avalanche diode (RE-SPAD) array, are presented. A custom-developed technology has been exploited to design a detector having large-area pixels (50-μm diameter) with optimized performance. With an excess bias voltage Vov = 15 V, a photon detection efficiency as high as 57% at 600 nm (33% at 800 nm) is achieved, along with a dark count rate in the kHz range and optical crosstalk probability as low as 0.29%. The remarkable detection efficiency of the RE-SPAD array makes the module particularly suitable for all applications where high-detection efficiency in the red/near-infrared range is mandatory. As an example, the performance of the array module is demonstrated to match the demanding requirements of multispot single-molecule fluorescence spectroscopy. [ABSTRACT FROM AUTHOR]

Time-correlated single-photon counting (TCSPC) is a powerful optical technique, which permits recording fast luminous signals with picosecond precision. Unfortunately, given its repetitive nature, TCSPC is recognized as a relatively slow technique, especially when a large time-resolved image has to be recorded. In recent years, there has been a fast trend toward the development of TCPSC imagers. Unfortunately, present systems still suffer from a trade-off between number of channels and performance. Even worse, the overall measurement speed is still limited well below the saturation of the transfer bandwidth toward the external processor. We present a routing algorithm that enables a smart connection between a 32 × 32 detector array and five shared high-performance converters able to provide an overall conversion rate up to 10 Gbit/s. The proposed solution exploits a fully digital logic circuit distributed in a tree structure to limit the number and length of interconnections, which is a major issue in densely integrated circuits. The behavior of the logic has been validated by means of a field-programmable gate array, while a fully integrated prototype has been designed in 180-nm technology and analyzed by means of postlayout simulations. [ABSTRACT FROM AUTHOR]

In this letter, we demonstrate a dynamic range as high as 152 dB with a detection head based on a single-photon avalanche diode (SPAD). This result has been attained by exploiting two key factors: on one hand, the low dark count rate (9 cps) of a custom-technology SPAD; and on the other hand, the maximum count rate (120 Mcps) achievable with a new generation active quenching circuit and an optimized assembly of the system. To the best of our knowledge, this is the highest dynamic range reported so far in the literature for a SPAD. Even more important, this value has been attained without sacrificing other detector parameters, such as active area diameter (50 μm), photon detection efficiency (50% at 550-nm wavelength), and afterpulsing probability (2%). [ABSTRACT FROM AUTHOR]

In recent years, time-correlated single photon counting (TCSPC) has become the technique of choice in many life science analyses, where fast and faint luminous signals are recorded with picosecond accuracy. Nevertheless, the maximum operating frequency of a single TCSPC acquisition channel limits the measurement speed, especially when scanning point systems are exploited. In order to increase the speed of TCSPC experiments, many multichannel systems based on single photon avalanche diode arrays have been proposed in the literature, which integrate thousands of pixels on the same chip. Unfortunately, the huge number of data generated by this kind of system can easily bring to the saturation of the transfer bandwidth to the external processing unit. For this reason, several different readout architectures have been proposed in the literature, attempting to exploit at best the limited bandwidth under TCSPC operating conditions. In this paper, some typical readout approaches, namely clock-driven and event-driven readouts, are discussed and compared, along with a recently-introduced router-based algorithm that is specifically designed to obtain maximum bandwidth exploitation under any condition. Quantitative comparisons are performed starting from imager response of the systems, which is the rate of recorded events in the case of uniform illumination of the detector array. [ABSTRACT FROM PUBLISHER]

We describe an 8-spot confocal setup for high-throughput smFRET assays and illustrate its performance with two characteristic experiments. First, measurements on a series of freely diffusing doubly-labeled dsDNA samples allow us to demonstrate that data acquired in multiple spots in parallel can be properly corrected and result in measured sample characteristics consistent with those obtained with a standard single-spot setup. We then take advantage of the higher throughput provided by parallel acquisition to address an outstanding question about the kinetics of the initial steps of bacterial RNA transcription. Our real-time kinetic analysis of promoter escape by bacterial RNA polymerase confirms results obtained by a more indirect route, shedding additional light on the initial steps of transcription. Finally, we discuss the advantages of our multispot setup, while pointing potential limitations of the current single laser excitation design, as well as analysis challenges and their solutions. [ABSTRACT FROM AUTHOR]

In recent years, single-photon timing techniques have been employed in a steadily increasing number of applications. Most of these applications require high detector performance in terms of noise, photon detection efficiency, time resolution, and number of pixels operating in parallel. The detectors best fitting these requirements are single-photon avalanche diode (SPAD) arrays built in custom technology, although the systems based on such detectors are limited to a few pixels. In this paper, we present a novel read-out circuit, developed in a 0.18- $\mu $ m high voltage-CMOS technology, for the detection of the SPAD avalanche current: the designed circuit is based on a 2.2-GHz bandwidth integrated transimpedance amplifier, followed by a low-pass filter, to reduce crosstalk, and by an integrated comparator. The pick-up circuit has a total power dissipation of 1.1 mW, occupies an overall area of 15500 \mu $ \mathrm{m}^{2} and shows a time resolution down to 48 ps and a negligible crosstalk between two different pixels. All these features can open the way to the development of large SPAD arrays, characterized by a performance comparable with that of the single-pixel structures. Moreover, the good agreement between the simulated and the measured resolution (with a 14% maximum error) makes the future improvement of the evaluated performance possible. [ABSTRACT FROM AUTHOR]

Single-molecule Förster resonance energy transfer (smFRET) allows measuring distances between donor and acceptor fluorophores on the 3–10 nm range. Solution-based smFRET allows measurement of binding-unbinding events or conformational changes of dye-labeled biomolecules without ensemble averaging and free from surface perturbations. When employing dual (or multi) laser excitation, smFRET allows resolving the number of fluorescent labels on each molecule, greatly enhancing the ability to study heterogeneous samples. A major drawback to solution-based smFRET is the low throughput, which renders repetitive measurements expensive and hinders the ability to study kinetic phenomena in real-time. Here we demonstrate a high-throughput smFRET system that multiplexes acquisition by using 48 excitation spots and two 48-pixel single-photon avalanche diode array detectors. The system employs two excitation lasers allowing separation of species with one or two active fluorophores. The performance of the system is demonstrated on a set of doubly labeled double-stranded DNA oligonucleotides with different distances between donor and acceptor dyes along the DNA duplex. We show that the acquisition time for accurate subpopulation identification is reduced from several minutes to seconds, opening the way to high-throughput screening applications and real-time kinetics studies of enzymatic reactions such as DNA transcription by bacterial RNA polymerase. [ABSTRACT FROM AUTHOR]

This paper describes an eight-channel differential pulse generator based on a fast differential bipolar transistor output stage. It has been designed specifically to test new multichannel time-correlated single-photon counting (TCSPC) instruments, while maintaining a wide range of regulation possibilities in terms of frequency, amplitude, delay, and duty cycle. The input signal for each channel can be provided either by an on-board programmable frequency synthesizer or by an external reference shared by all channels. The chosen input is delivered to a delayer loop controlled by a field programmable gate array (FPGA), which provides the desired delay, minimizing the jitter contribution. The delayed signal is fed to an analog differential stage that provides the fast output, whose amplitude and offset are adjusted by a digital-to-analog converter, controlled by the FPGA. The experimental results on the instrument show an output slew rate of 1600 V/ \mu \texts over the complete full-scale range, which is between −2 and 6 V. The feedback delayer regulates the delay between 0 ns and 30 \mu \texts whereas the high time is adjustable from a minimum of 10 ns to a maximum of 30 \mu \texts . Finally, the frequency range is from 2 kHz to 50 MHz. All these adjustable parameters are managed by a microcontroller that works as an interface between the FPGAs and dedicated PC software. The implemented structure allows the system to achieve a time resolution down to 6 ps across all channels, making this instrument perfect for testing high time resolution TCSPC systems. [ABSTRACT FROM PUBLISHER]

Timing measurements with silicon photomultipliers (SiPMs) are affected by the major issue of the so‐called time‐walk effect; this is due to the intrinsic architecture of SiPM devices. A new technique for time‐walk compensation in timing measurements with SiPMs is presented and discussed, feasible with a low‐complexity and low‐cost circuitry and able to improve the timing accuracy. The validity of the presented technique has been experimentally proven with a 3 × 3 mm2 Hamamatsu MPPC, achieving a jitter reduction of a factor 2.85 compared with the case without time‐walk compensation. To perform the experimental validation, a discrete‐components transimpedance amplifier is developed with large bandwidth and low jitter, specifically designed to read‐out and amplify the SiPM signal. [ABSTRACT FROM AUTHOR]

Modern time-correlated single-photon counting (TCSPC) systems can achieve very high performance, but advanced applications also demand the implementation of multichannel acquisition chains. To fit the specifics of TCSPC applications we developed a complete single-channel measurement system, composed by three main parts: a single-photon detection module, a TCSPC acquisition board and a power management unit. The system is based on a single-photon avalanche diode (SPAD) and on a fully integrated time-to-amplitude converter (TAC). We designed the module to be very compact, in order to be enclosed in a small case (110 × 50 × 40 mm). The system features high temporal resolution (71 ps), low differential nonlinearity (0.05 LSB), high counting rate (4 MHz) and low power. Moreover a four-channel TAC has already been manufactured and tested; the very low crosstalk between channels, together with low power and low area make the converter suitable for large scale multi-channel acquisition chains, allowing the implementation of architectures for multidimensional TCSPC measurements. [ABSTRACT FROM PUBLISHER]

Recently, a growing interest has arisen about the time-correlated single photon counting (TCSPC) technique, that allows the analysis of fast and weak light waveforms with a time resolution in the picosecond order. Since TCSPC basically consists of the measurement of the arrival time of a photon, a high resolution and high linearity time measurement block is of the utmost importance; moreover, the use of multianode Photo Multiplier Tube and of single photon avalanche diode arrays led to the development of multichannel acquisition systems, where the time measurement block has to be integrated to reduce both cost and area. We have designed and fabricated a four channel fully integrated time-to-amplitude converter (TAC), built in 0.35 \mum Si-Ge technology, characterized by an excellent time resolution (less than 50 ps full width half maximum), low differential nonlinearity (better than 0.02 LSB peak-peak and 0.0003 LSB rms), high counting rate (16 MHz), low and constant power dissipation (50 mW) and low area occupation (2.58\,\times\,1.28 mm^2). Moreover, the very low crosstalk (-115 dB) between channels, together with low power and low area makes the converter suitable for large scale multi-channel acquisition chains. [ABSTRACT FROM AUTHOR]

We present a detailed analysis of a gigahertz clock rate environmentally robust phase-encoded quantum key distribution (QKD) system utilizing several different single-photon detectors, including the first implementation of an experimental resonant cavity thin-junction silicon single-photon avalanche diode. The system operates at a wavelength of 850 nm using standard telecommunications optical fibre. A general-purpose theoretical model for the performance of QKD systems is presented with reference to these experimental results before predictions are made about realistic detector developments in this system. We discuss, with reference to the theoretical model, how detector operating parameters can be further optimized to maximize key exchange rates. [ABSTRACT FROM AUTHOR]

In recent years, time-correlated single-photon counting techniques have been applied to time-of-flight measurements for long-distance range-finding and depth imaging. Depth imaging has been performed by obtaining timing information from an individual single-photon detector and scanning the optical field to obtain a full depth image. Typically, the measurement is made by dwelling on each individual depth pixel for a pre-defined integration time and completing the data acquisition for that pixel before steering the beam to the adjacent spatial position. We present a novel photon-counting data acquisition mode where the time-of-flight histograms for each depth pixel are gradually populated. The system repeatedly scans the same spatial frame with short per-pixel dwell times, and sufficient photon statistics are built up over many frames by cumulating photon events from all acquired frames. The technique is used to compare the depth imaging performance of two single-photon avalanche diode detectors: a novel, resonant-cavity enhanced shallow-junction device; and a commercially available thick-junction device. [ABSTRACT FROM AUTHOR]

Over the past few years there has been a growing interest in monolithic arrays of single photon avalanche diodes (SPADs) for parallel detection of faint ultrafast optical signals. SPADs implemented in CMOS-compatible planar technologies offer the typical advantages of microelectronic devices (small size, ruggedness, low voltage, low power, etc.). Furthermore, they have inherently higher photon detection efficiency than photomultiplier tubes and they are able to provide very high acquisition speeds. The development of fully-parallel multichannel systems is a challenge both for the detector (with new problems like optical and electrical crosstalk, isolation elements size reduction and the need for higher yields) and for the electronics. The development of a parallel detector must be accompanied by that of the time-to-amplitude converters and analysis electronics necessary in time-correlated single photon counting applications. In this paper we present the fundamental building blocks necessary to develop a parallel picosecond array detector: a new high-performance SPAD detector, compatible with the design of multi-detector systems with a large number of channels, and a new totally integrated system for time-to-amplitude conversion, to allow the simple integration of several channels on a single chip. [ABSTRACT FROM AUTHOR]

In recent years, a growing number of applications demand better timing resolution from single-photon avalanche diodes (SPADs). The challenge is pursuing improved timing resolution without impairing other device characteristics such as quantum efficiency and dark count rate. This task requires a clear understanding of the statistical phenomena involved in the avalanche current growth in order to drive the device engineering process. Past studies state that in Si SPADs the avalanche injection position statistics is the main contribution to the photon-timing jitter. However, in recent re-engineered devices, this assumption has been questioned. To address this issue, we developed an experimental setup capable of characterizing the photon-timing jitter as a function of the injection position by means of a laser focused on the device active area. The results not only confirmed that the injection position statistics is not the main contribution to photon-timing jitter, but also evidenced interesting dependences of the timing performances on the injection position. Furthermore, we found a relationship between the photon-timing jitter and the specific resistance of the devices, which has been investigated by means of photoluminescence measurements. [ABSTRACT FROM PUBLISHER]

In free-space single-photon quantum key distribution (QKD), the error rate due to daytime background photons can be reduced with strong temporal filtering. In this case, the improvement in performance is determined by the receiver's ability to resolve signal-photon arrival times. We use fast clock recovery and commercially available single-photon detectors with timing resolution enhanced by additional electronic circuitry to implement temporal gating down to 50 ps in a free-space QKD system. The single-photon channel operates at 850 nm, and the improved timing resolution enables transmission rates of 1.25 GHz. We observe daytime quantum bit error rates of 0.04, which is less than one-third of the ungated error rate. We present the design and performance of the system and demonstrate its benefit to free-space QKD. [ABSTRACT FROM PUBLISHER]

We report the first resonant-cavity-enhanced single photon avalanche diode (RCE SPAD) fabricated on a reflecting silicon-on-insulator (SOI) substrate. The substrate incorporates a two period distributed Bragg reflector fabricated using a commercially available double SOI process. The RCE SPAD detectors have peak photon detection efficiencies ranging from 42% at 780 nm to 34% at 850 nm and an excellent photon timing resolution of 35 ps full width at half maximum. Despite the higher defectivity of double SOI substrates compared to standard silicon substrates, RCE SPADs with 20 µm diameter exhibit a fairly low dark count rate (DCR) of 3500 cs-1 at room temperature and a yield of 80%. A DCR less than 50 cs-1 can be attained with these detectors by reducing the temperature down to -15°C, while keeping the total afterpulsing probability below 9% with a dead-time of 80 ns. [ABSTRACT FROM AUTHOR]

In life science, optical techniques for the characterization of biological processes are well established and widely used. In most of them, to obtain the best performances, detectors with single-photon detection capability are required. Moreover, the growing demand for this type of information is pushing the technology towards a parallelization of the analysis. These requirements make it very challenging to develop new detection heads, because state-of-the-art detectors, such as photomultiplier tubes (PMTs) and charged coupled devices (CCDs), have some drawbacks. For example, in fluorescence correlation spectroscopy (FCS) fluorescence fluctuations must be monitored on a short time scale because typical time constants range from hundreds of nanoseconds to milliseconds. In this case, developing parallel modules for this application is very challenging. In fact, PMTs are bulky and they cannot be integrated, while the use of imaging detectors, such as CCDs and electron multiplying CCDs, is strongly limited by the read time that determines the minimum correlation time detectable by FCS analysis. We present here a multichannel photon counting module that exploits a monolithic array of single-photon avalanche diodes (SPADs). The detector array consists of eight 50 µm diameter SPADs featuring low dark counting rate and high photon detection efficiency (50% at 550 nm); inter-pixel crosstalk probability is as low as 2 × 10-3. The use of highly integrated active quenching circuits makes it possible to design a very compact read-out circuit, yet providing eight fully independent counting channels operating at high count rate (up to 30 million counts per second). Parallel-mode operation, high count rate and low-cost make this module a potential breakthrough for a widespread diffusion of FCS analysis. [ABSTRACT FROM AUTHOR]

This paper investigates the application of a mixed-signal synchronous/asynchronous digital controller to dc-dc boost converters. The digital control synchronously generates current and voltage ramps by using two low-resolution digital-to-analog converters. The switch turn-on and turn-off are determined asynchronously by comparing the converter-state variables and the digitally generated current and voltage ramps. The control features high dynamic performance, frequency modulation during transients, small quantization effects, and low complexity. In order to evaluate the dynamic performance and compare the proposed solution with conventional analog peak-current-mode control, a small-signal model of the synchronous/asynchronous modulation is derived. Even if aimed to an integrated digital controller, experimental investigation has been performed by using discrete components, implementing the digital control in a field-programmable gate array by using a VHDL. The simulation and experimental results on 100-W dc-dc boost converter confirm the proposed analysis and show that the proposed solution enables a dynamic performance that is comparable with that of analog peak-current-mode control. [ABSTRACT FROM AUTHOR]

This paper investigates power line communication (PLC) in digitally controlled high-frequency switched-mode power supplies in distributed architectures that share the same bus voltage. Communication between different dc-dc converters is obtained by using switching frequency modulation and by detecting the switching signal on the common supply bus voltage. In case of low power transmission, a small duty-cycle perturbation at half of switching frequency is added to enhance the energy of the transmitted signal. Each converter operates at three different switching frequencies: the first is associated with bit 1 transmission, the second is associated with bit 0 transmission, and the third is associated with no transmission state. In the proposed solution, there is no need for an additional power amplifier in order to inject the communication signal on the power lines, but the signal used for the PLC is inherently generated by the pulsewidth modulation of dc-dc converters. Even if aimed at a dedicated digital IC, the communication architecture has been implemented in field- programmable gate arrays. Simulation and experimental results on dc-dc synchronous buck converters confirm that the performance is achievable by the proposed PLC techniques. [ABSTRACT FROM AUTHOR]

A 48-element monolithic matrix detector, designed for parallel fluorescence detection, has been fabricated in silicon and tested. The pixels are single photon avalanche diodes (SPADs) with 50 µm diameter, ordered in a 6× 8 array with 240 µm pitch. The photon detection efficiency is remarkably uniform over the array: it has a peak of 48% at 530 nm and it is higher than 30% over all the visible range. Low dark counting rate (DCR) is obtained in operation at moderately low temperature (-15°C with thermoelectric cooling): the individual pixel DCR is 60 c s-1 for about 40% of the elements and it is below 5700 c s-1 in the rest of the array. It was verified that the afterpulsing probability is below 1% and that the optical crosstalk probability between elements is lower than 0.2%. Based on this matrix detector, we have developed a versatile and compact (20 cm× 8 cm × 4 cm) photon counting module that can be easily interfaced to a PC via USB link. [ABSTRACT FROM AUTHOR]

Experimental results obtained with silicon single photon avalanche diodes (SPADs) in quantum key distribution (QKD) at short wavelengths reveal remarkable potential for application in local area networks (LAN) and for free-space transmission at high rate. Actual application prospects, however, depend on the performance level and on the suitability of practical systems using the available silicon SPAD devices. They can be essentially divided in two groups: planar p-n junction structures with a thin depletion layer (typically 1 μm); and reach-through structures with a thick depletion layer (from 20 μm to 150 μm). The physical mechanisms that control the device behaviour were investigated and the effect on the key parameters of the detector (quantum detection efficiency, dark counting rate, afterpulsing probability and photon-timing jitter) were thoroughly assessed. A quantitative analysis was made of the influence of such parameters on the quantum bit error rate (QBER). Actual parameters were measured and the attainable performance and system suitability of the two device types evaluated. Comparable performance is obtained, but from a system viewpoint thin SPADs appear inherently better suited to high-rate QKD applications, because of their faster response time, ruggedness, low voltage, low power dissipation and fabrication technology, which is simple, efficient, economical and compatible with monolithic integration of detector and associated circuits. [ABSTRACT FROM AUTHOR]

Presents a study which manufactured high-sensitivity solid-state detectors designed for measurements in laser scanning microscopy. Discussion on laser scanning microscopy; Description of photodetectors structures; Results and discussion; Conclusions.