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Active mobility and light vehicles, such as e-bikes, are gaining increasing attention as sustainable transportation alternatives to internal combustion solutions. In this context, collecting comprehensive data on environmental conditions, vehicle performance, and user interaction is crucial for improving system efficiency and user experience. This paper presents a data acquisition system designed to collect data from multiple sensor platforms. The architecture is optimized to maintain low power consumption and operate within limited computational resources, making it suitable for real-time data acquisition on light vehicles. To achieve this, a data acquisition module was developed using a single-board computer integrated with a custom shield, which also captures data related to the assistance of an e-bike motor through a wireless interface. The paper provides an in-depth discussion of the architecture and software development, along with a detailed overview of the sensors used. A demonstrator was created to verify the system architecture idea and prove the potentialities of the system overall. The demonstrator has been qualified by professional and semi-professional riders in the framework of the Giro-E, a cyclist event which took place in May 2024, on the same roads of the Giro d'Italia. Finally, some preliminary analyses on the data acquired are provided to show the performance of the system, particularly in reconstructing the user behavior, the environmental parameters, and the type of road. [ABSTRACT FROM AUTHOR]

Light and active mobility, as well as multimodal mobility, could significantly contribute to decarbonization. Air quality is a key parameter to monitor the environment in terms of health and leisure benefits. In a possible scenario, wearables and recharge stations could supply information about a distributed monitoring system of air quality. The availability of low-power, smart, low-cost, compact embedded systems, such as Arduino Nicla Sense ME, based on BME688 by Bosch, Reutlingen, Germany, and powered by suitable software tools, can provide the hardware to be easily integrated into wearables as well as in solar-powered EVSE (Electric Vehicle Supply Equipment) for scooters and e-bikes. In this way, each e-vehicle, bike, or EVSE can contribute to a distributed monitoring network providing real-time information about micro-climate and pollution. This work experimentally investigates the capability of the BME688 environmental sensor to provide useful and detailed information about air quality. Initial experimental results from measurements in non-controlled and controlled environments show that BME688 is suited to detect the human-perceived air quality. CO2 readout can also be significant for other gas (e.g., CO), while IAQ (Index for Air Quality, from 0 to 500) is heavily affected by relative humidity, and its significance below 250 is quite low for an outdoor uncontrolled environment. [ABSTRACT FROM AUTHOR]

This paper presents the design and characterization of a miniaturized wearable electronic system for photoplethysmography. The system is conceived with the purpose of monitoring people during their normal duties or during physical activity. An in-depth investigation of its performance has been carried out to address the main parameters affecting signal quality. Moreover, an investigation of the best body measurement location has been assessed. [ABSTRACT FROM AUTHOR]

This paper is concerned with the design of a Charge Sensitive Amplifier (CSA) in a 28 nm CMOS technology. The CSA discussed in this work is conceived for High Energy Physics (HEP) experiments at next-generation colliders, where pixel detectors will be read out by specific front-end chips, typically including a CSA exploited for charge-to-voltage conversion of the signal delivered by the sensor. The main analog performance parameters of the CSA, also referred to as the pre-amplifier, are assessed here by means of specific Spectre simulations, which are meant to evaluate the behavior of the analog processor in terms of noise, linearity and capability to compensate for very large detector leakage currents. Noise simulations revealed an equivalent noise charge close to 75 electrons rms for typical operating conditions. Up to 50 nA sensor leakage current can be compensated for thanks to the CSA Keummenacher feedback network. The total current consumption of the CSA is close to 2.2 µA, which, together with a power supply of 0.9 V, translates to a power consumption of 2.0 µW. [ABSTRACT FROM AUTHOR]

Irradiation tests on 90 nm CMOS devices at different total ionizing doses lead to new insights into degradation mechanisms in gate oxides and lateral isolation structures and into their impact on gate and drain current noise sources. The action of lateral parasitic transistors and their physical parameters are studied in different operating conditions. The main focus is on 1/f noise, which is one of the few parameters which are sizably affected by irradiation. Irradiation effects on the noise in the gate current are discussed in this paper for the first time. The analysis of the behavior of thick oxide I/O transistors provides a comparison both with thin oxide core devices and with previous, less scaled CMOS generations. Index Terms--Deep submicron, ionizing radiation, MOSFET, noise, shallow trench isolation (STI).

This paper is motivated by the growing interest of the detector and readout electronics community towards silicon-on-insulator CMOS processes. Advanced SOI MOSFETs feature peculiar electrical characteristics impacting their performance with respect to bulk CMOS devices. Here we mainly focus on the study of these effects on the noise parameters of the transistors, using experimental data relevant to 180 nm fully depleted SOI devices as a reference. The comparison in terms of white and 1/f noise components with bulk MOSFETs with the same minimum feature size gives a basis of estimate for the signal-to-noise ratio achievable in detector front-end integrated circuits designed in an SOI technology. Index Terms--Front-end electronics, MOSFET, noise, silicon-on-insulator.

The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(Si[O.sub.2]) [gamma]-ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(Si[O.sub.2])) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point. Index Terms--Ionizing radiation, deep submicron CMOS, thermal noise, flicker noise.

The CERN RD53 collaboration was founded to tackle the extraordinary challenges associated with the design of pixel readout chips for the innermost layers of particle trackers at future high energy physics experiments. Around 20 institutions are involved in the collaboration, which has the support of both ATLAS and CMS experiments. The goals of the collaboration include the comprehensive understanding of radiation effects in the 65 nm technology, the development of tools and methodology to efficiently design large complex mixed signal chips and, ultimately, the development of a full size readout chip featuring a 400 × 400 pixel array with 50 μ m pitch. In August 2017, the collaboration submitted the large scale chip RD53A, integrating a matrix of 400 × 192 pixels and embodying three different analog front-end designs. This work discusses the characteristic of the RD53A chip, with some emphasis on the analog processors, and presents the first test results on the pixel array. • High particle rates and radiation levels will be reached at the HL-LHC. • New pixel chips for the phase II upgrades of CMS and ATLAS are required. • The RD53A chip has been designed in the framework of the RD53 Collaboration. • Three analog front-ends flavors are integrated in RD53A. • The paper presents the main preliminary results coming from RD53A characterization. [ABSTRACT FROM AUTHOR]

A charge preamplifier has been developed in a 65-nm CMOS technology for processing the signals from the inner pixel layers of the CMS detector, in view of the experiment upgrade for the High-Luminosity (HL) Large Hadron Collider (LHC). The circuit is part of a readout channel implementing a time-over-threshold method for the analog-to-digital conversion of the input charge signal. Samples of the circuit have been exposed to high doses of ionizing radiation, up to 500 Mrad(SiO2), from a low-energy proton source and from an X-ray tube. The test results show that the performance degradation, in terms of charge sensitivity, signal shape, and noise, is compatible with operation in the harsh environment of the HL-LHC. Measurement data from the characterization of preamplifiers using different kinds of capacitors in the feedback network help to gain some insight into the damage mechanisms in pMOS transistors irradiated with large ionizing doses. The dependence of performance degradation on the kind of radiation source used in the tests is also discussed. [ABSTRACT FROM PUBLISHER]

This work is concerned with the design of a low-noise Charge Sensitive Amplifier featuring a dynamic signal compression based on the non-linear features of an inversion-mode MOS capacitor. These features make the device suitable for applications where a non-linear characteristic of the front-end is required, such as in imaging instrumentation for free electron laser experiments. The aim of the paper is to discuss a methodology for the proper design of the feedback network enabling the dynamic signal compression. Starting from this compression solution, the design of a low-noise Charge Sensitive Amplifier is also discussed. The study has been carried out by referring to a 65 nm CMOS technology. [ABSTRACT FROM AUTHOR]

This work is concerned with the study of the analog properties of MOSFET devices belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise performance. This node appears to be a robust and promising solution to cope with the unprecedented requirements set by silicon vertex trackers in experiments upgrades and future colliders as well as by imaging detectors at light sources and free electron lasers. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. An inversion level design methodology has been adopted to analyze data obtained from device measurements and provide a powerful tool to establish design criteria for detector front-ends in this nanoscale CMOS process. A comparison with data coming from less scaled technologies, such as 90 nm and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range. [ABSTRACT FROM PUBLISHER]

This work presents the characterization of deep n-well (DNW) CMOS monolithic active pixel sensors (MAPS) fabricated in a 130 nm homogeneous, vertically integrated technology. An evaluation of the 3D MAPS device performance, designed for application of the experiments at the future high luminosity colliders, is provided through the characterization of the prototypes, including tests with infrared (IR) laser, ^55Fe and ^90Sr sources. The radiation hardness study of the technology will also be presented together with its impact on 3D DNW MAPS performance. [ABSTRACT FROM PUBLISHER]

Total ionizing dose effects are studied in 130-nm transistors and pixel sensors in a vertically integrated two-layer CMOS technology, evaluating the possible impact of 3D integration on radiation tolerance and damage mechanisms. Measurements of static characteristics and noise voltage spectra before and after exposure to high total ionizing doses demonstrate that the analog performance of transistors as well as their radiation hardness are not degraded by mechanical and thermal stresses occurring during the fabrication of the 3D chips. The paper also presents irradiation results on 3D CMOS pixel sensors with a sparsified readout architecture. After exposure to ionizing radiation, these devices behave in a very similar way as analogous counterparts in a standard 2D 130-nm process, confirming that performance advantages associated with 3D integration are not impaired by an enhanced radiation sensitivity. [ABSTRACT FROM PUBLISHER]

A model, approximating minority carrier diffusion with a discrete random walk and accounting for radiation induced reduction of minority carrier lifetime, is proposed to predict the effects of neutron irradiation on the charge collection properties of monolithic active pixel sensors (MAPS) in CMOS technology. The model has been implemented in a Monte Carlo code to simulate MAPS operation in minimum ionizing particle detection systems. For the purpose of validating it, the results from the characterization of monolithic sensors irradiated up to an integrated fluence of 10^14 1-MeV-neutron\ equivalent/cm^2 have been compared with the outcomes of the Monte Carlo simulations. The monolithic sensors taken into consideration for the model validation are based on two different CMOS processes, one featuring a triple well option, the other one featuring a quadruple well structure and a standard (10 \Omega\cdotcm) or high (1 k\Omega\cdotcm) resistivity epitaxial layer. Simulation results are shown to be in good agreement with experimental data. The consistency between the model and the measurement results seems to confirm that radiation induced increase in the recombination rate is the main source of charge collection degradation in neutron-irradiated MAPS. [ABSTRACT FROM AUTHOR]

Apsel4well is a monolithic active pixel sensor (MAPS) chip intended for application to fast and low material silicon vertex trackers for future experiments at high intensity machines. The design is based on a 180 nm CMOS process with quadruple well option called INMAPS. This technology makes it possible to increase the in-pixel intelligence as compared to standard three transistor MAPS and their variants. Moreover, the availability of a high resistivity epitaxial layer is confirmed to lead to further improvements in terms of charge collection performance and radiation resistance. This paper, after providing some details on the INMAPS process, focuses on the analog front-end section of the pixel readout chain. Measurement results on the main analog channel parameters, like charge sensitivity and equivalent noise charge, are given along with charge collection properties evaluation through ^90Sr/^90Y spectrum measurements and laser stimulation. Characterization data were also used for validating a TCAD model of the device. Finally, selected results from a neutron irradiation campaign with fluences up to 2.7\times 10^13 1 MeV neutron equivalent/cm^2 will be shown. [ABSTRACT FROM PUBLISHER]

This work is concerned with the design criteria and the experimental characterization of front-end electronics in a 65-nm CMOS technology for the readout of hybrid pixels and of monolithic active pixel sensors using a deep N-well as their collecting electrode. The work presents a summary of the experimental results relevant to a prototype chip, named Apsel65, focusing particularly on the front-end processor features and performance. [ABSTRACT FROM AUTHOR]

This paper is concerned with the study of the total ionizing dose (TID) effects in NMOS transistors belonging to 90 and 65 nm CMOS technologies from different manufacturers. Results from static and noise measurements are used to collect further evidence for a static and noise degradation model involving charge buildup in shallow trench isolations and lateral parasitic transistor activation. Comparison between two CMOS processes both belonging to the 90 nm node but coming from different foundries makes it possible to shed some light on the process-dependent features of the device response to ionizing radiation. [ABSTRACT FROM AUTHOR]