1. A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing
- Author
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Y. Suzuki, T. Kirihata, M. Nishiwaki, R.L. Franch, K. Kitamura, T.V. Rajeevakumar, Y. Iguchi, S.H. Dhong, Walter H. Henkels, Wei Wang, Yasunao Katayama, Gary B. Bronner, F.L. Pesavento, H. Niijima, Y. Sakaue, E. Yano, Roy Edwin Scheuerlein, and N. C.C. Lu
- Subjects
Engineering ,Hardware_MEMORYSTRUCTURES ,business.industry ,Electrical engineering ,Hardware_PERFORMANCEANDRELIABILITY ,Integrated circuit ,Chip ,Multiplexing ,PMOS logic ,law.invention ,CMOS ,law ,Hardware_INTEGRATEDCIRCUITS ,Electrical and Electronic Engineering ,business ,Random access ,Dram ,Access time - Abstract
Describes a 1-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A double-polysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3- mu m feature size. The chip has also been fabricated in a 0.9*shrunken version with an area of 67 mm/sup 2/, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAMs to be used in a broad new range of applications. >
- Published
- 1989
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