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This paper presents a novel procedure for detecting offset, gain, and timing skew errors in foreground calibration of time‐interleaved analog‐to‐digital converters (TI‐ADCs). An efficient peak detection scheme has been introduced, which is successfully employed to extract timing skew error. The designed method has also been extended to derive the gain and offset errors separately to form the generalized architecture. The objective is performed with the adjustment of the rational coefficient for each error. Simplicity and low hardware consumption will constitute the notable advantages of the proposed algorithm. Mathematical expressions have been provided to explain the principles. A special case in which all triple errors could exist together has also been analyzed. Then, the proposed architecture was implemented at the system level. Finally, the behavioral simulation results for a 12‐bit four‐channel TI‐ADC have been demonstrated to confirm the accuracy of the proposed algorithm. The simulation environment has consisted of the sampling frequency of 8 GHz for TI‐ADC and 1 GHz single‐tone input frequency for each channel (associated with the Gaussian noise). Based on the results, the maximum value of 77.21 dB for SFDR has been achieved after the calibration process when the average error of 9% for timing skew and 6% tolerance for gain were considered for the channels of TI‐ADC. [ABSTRACT FROM AUTHOR]

In this brief, a novel scheme for the derivation of triple errors associated with Time-Interleaved Analog-to-Digital Converters (TI-ADCs) has been presented. This algorithm relies on the utilization of reference Analog-to-Digital Converter (ADC) for the background calibration process. The main advantage of the proposed architecture is that it provides the possibility to calibrate offset, gain and timing skew by utilization of a simple structure. The objective has been accomplished by adjusting the corresponding coefficients of each error. At first, the main idea has been introduced by mathematical expressions. Then, the architecture for extraction of each error has been derived from the calculations, and the generalized scheme has been demonstrated which extracts the errors. Finally, system-level simulations were provided to indicate the correct behavior of the proposed algorithm for a 12-bit 4-channel TI-ADC. Based on simulation results, the maximum value of 81dB for SFDR after calibration process has been achieved when an average error of 11ps was considered for each channel at the sampling frequency of 8GHz and 1GHz single tone input frequency. Also, the corresponding maximum value for SNDR is 66dB. [ABSTRACT FROM AUTHOR]

Estimation of localization error and selection of system parameters are the key factors in evaluation of visual 3-D systems. Iso-disparity layers and correspondence field are recently introduced to present a graphical model for space sampling in general 3-D systems. The correspondence field describes the spatial topology of the intersecting rays of cameras, arranged in a number of layers or surfaces with same disparity values, referred as iso-disparity layers. This paper develops a mathematical framework to investigate the geometrical variations of these layers with respect to camera intrinsic and extrinsic parameters. It will be demonstrated that the layers in their general form appear as a set of quadric surfaces, where the coefficients of these quadrics depend on system parameters. The distance between the iso-disparity layers due to the quantization process is suggested as a measure of uncertainty and can be considered as a criterion for appropriate selection of parameters, such as focal length, position, and orientation of cameras for the system to achieve desirable precision. Here, we use an analytical solution to calculate the orthogonal distance between the two successive iso-disparity layers. These distances are representatives of depth uncertainty. Finally, we have simulated our model and the results verify that the total average error is less than 2%. [ABSTRACT FROM PUBLISHER]