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This paper gives an overview of a collector-emitter voltage sign-based commutation method. This method is implemented based on the output current sign and commutation voltage polarity signals of matrix converter. All these signals are acquired by a simple unit in the drive and protection boards designed for reverse blocking insulated gate bipolar transistors (RB-IGBTs) of the matrix converter in test. Therefore, no current and/or voltage sensor is required to obtain any other commutation signals. The RBIIGBT samples used are newly developed, and one important feature is that its reverse leakage current is mostly affected by [v.sub.ge]. Under the same temperature condition, when [v.sub.ce] is negative, a positively biased [v.sub.ge] results in a distinct decrease of the reverse leakage current. The proposed commutation method can supply the reverse-blocked RB-IGBTs with positively biased [v.sub.ge]. Hence, the power losses caused by the reverse leakage current can be reduced using the proposed method. Experimental results have proved the feasibility and effectivity of this method. Index Terms--Commutation, matrix converter, reverse blocking insulated gate bipolar transistor (RB-IGBT), reverse leakage current.

This paper illustrates a general method to formulate the equations for the analysis of commutations and of the effects caused by large step-wise perturbations, large change of parameters, and circuit failures in switching converters including transformers, feedback circuitry, and soft-switching cells. The matrix equations obtained by means of the modified nodal analysis--based method proposed in this work are useful for theoretical inspection of switching converters as well as for numerical simulations. The examples of applications concern the analysis and the synthesis of switching converters and show that the Compensation Theorem (CT)--based model may help in selecting circuit topologies valid for the circuit design.

A new thyristor current-source rectifier that achieves unity power factor, low-current total harmonic distortion (THD), and dc-bus current and voltage control is presented. The rectifier is suitable for high-power applications such as induction heating and dc arc furnaces. It combines a traditional six-pulse thyristor bridge and a dc chopper that together solve power quality problems such as poor power factor and flicker generation. This topology achieves low input current THD and dc power control without additional power-factor-correction equipment, harmonic trap filters, use of multiple pulse rectifiers, or high-K-factor transformers. Index Terms--Commutated circuits, pulsewidth-modulated power converters, rectifiers, thyristor converters.

A novel dc-link converter utilizing resonant commutation is presented. Since resonant commutation is accomplished, converter switches are thyristors (SCR's) with lower costs than forced commutated devices. Focus is on the variable-frequency operation of the converter, with potential application in variable-frequency custom power delivery or adjustable-speed motor drives. The converter operates with greater stored energy in the dc link, thus offering current holdup capabilities during a contingency which cannot be attained with a conventional resonant dc-link converter and achieves minimum switching losses without increased conduction losses. Harmonic elimination is achieved by employing sinusoidal pulsewidth modulation (SPWM) control of the converter. Simulation results and experimental validation of the resonant commutation of a low-voltage and low-power laboratory model are discussed. Work in progress and the scope of further work are discussed. Index Terms - Modulation index control, resonant commutation, resonant link converter, switching losses.

A new scheme of a soft-switched voltage-source inverter (VSI) capable of true pulse-width modulation (PWM) is presented. It utilizes inductors in series with the main switches to limit di/dt during turn on, while the inductor energy is recovered by a resonant turn-off process, which is allowed by the presence of two auxiliary switches. As inductive di/dt snubbers are usually needed in high-power gate-turnoff (GTO) converters, the proposed topology offers a solution to the problem of snubber energy recovery. The control strategy explained in the paper allows both full-range PWM and minimization of stresses during the resonant commutation process. Results of a theoretical analysis and design criteria are reported in the paper. Examples of PWM control schemes are also described, both for analog (ramp-comparison-based) and digital (space-vector-based) implementations. Experimental results obtained from a small-size laboratory prototype are given. Index Terms - Soft-switched inverters, voltage-source inverters, zero-current switching.

An analytical approach based on a two-dimensional electromagnetic field analysis in polar coordinates is developed to predict the commutation losses in a permanent magnet brushless dc (PMBD) motor. These losses are essentially the eddy-current losses induced in the PMBD motor's rotor magnets and core and are caused by the rotor sweeping of the stationary stator magnetic field before each current commutation due to inverter switching takes place. The approach is applicable to motor constructions with either magnet segments or a magnet ring and able to deal with ill-conditioned cases. The model was applied to an existing motor and good agreement (within 11%) with the finite element method was achieved. Index Terms - Analytical approach, commutation loss, eddycurrents, permanent-magnet brushless dc motors.

Load-commutated inverter (LCI) synchronous machine drives are common in the high power range. However, the starting performance of these systems is a concern since load-commutation can not occur at arbitrarily low speeds. This paper compares three different starting strategies including one apparently neglected method - normal load commutation. In particular, it is shown that depending on system parameters it may be possible to start the system with no special provision for start up. A method to determine whether a given system can be started using load commutation is presented.

The commutating safe operating area (CSOA) of DMOS FET's is determined by the peak reverse-recovery current and the peak reapplied voltage. Both contribute to the triggering of localized turn-on of the built-in bipolar junction transistor (BJT). New DMOS FET's with lower bipolar gain and shorter minority-carrier lifetime have doubled the CSOA capability.

The switched reluctance motor (SRM) is currently the focus of increasing attention because of its benign operational features and its attractive control mechanisms. Its fault tolerant features make the use of the SR machine convenient in applications requiring high reliability. This paper presents commutation schemes for most common types of SR motors. These schemes permit the realization of four-quadrant multimode SR motor drive operation with simple logic control and with position feedback from low-resolution position sensors.

This paper presents a method to determine the improved commutation position of a brushless DC (BLDC) motor in such a way as to generate the symmetric terminal voltages of the nonenergized phase at the beginning and end of the commutation period. If the BLDC motor is energized at the exact commutation position, the terminal voltage of the nonenergized phase at the beginning of commutation is equal to the terminal voltage at the end of commutation, and the waveform of the terminal voltage should be symmetric. This paper also develops a DSP-based sensorless BLDC motor controller to implement the proposed method and to verify its effectiveness experimentally. This research shows that the proposed method improves the performance of a BLDC motor by increasing torque and efficiency. Index Terms--Brushless DC motor, commutation, efficiency, sensorless control, torque.

A systematic approach to solve the open problem of finding multidimensional upsamplers and downsamplers that satisfy commutative conditions is derived. A test for conversion commutivity of conventional television signals to high definition television signals requires two matrices to be commutative and coprime, but this does not give a discovery process like the one presented. The solution is an algorithm in four steps.

A method and system are proposed for a transient-free commutation of a resonant-mode array of inductors. A single capacitor is used to tune the entire array, and triacs are used to accommodate the inductors.

This paper presents a computer aided model for the simulation of universal motor performance and brush commutation. The model consists of a set of flux linkage based differential equations. Time stepping integration method and 2D finite element field solutions are used for solving the system. An arcing model is introduced into the system to predict brush arcing and the arcing related energy. Computed results and test data are compared in the paper for a one armature coil per slot motor. Index Terms--2D finite element, apparent inductance matrix, arcing, brush-commutator contact resistance, brush resistance matrix, flux linkage, time stepping (FE).

The capacitive idling converters derived from the Cuk, SEPIC, Zeta, and Flyback topologies allow soft commutation of power switches without the need for additional circuitry, making it possible to increase the switching frequency while maintaining high efficiency. Index Terms - DC-DC power conversion, soft commutation, switching circuits.

Reduction of power consumption is significantly important for all high-performance digital VLSI systems. This paper reviews several approaches for low-power implementations of building blocks for digital subscriber line (DSL) systems. Low-power implementations of Reed-Solomon (RS) coders, fast Fourier transforms (FFTs), FIR filters, and equalizers, and reduction of power consumption by use of dual supply voltages are addressed. It is shown that use of separate Galois Field functional units for multiply-accumulate and degree reduction can reduce the energy consumption of RS coders dramatically. A hybrid feedforward and feedback commutator scheme-based FFT is shown to require less area and full hardware utilization efficiency. Reduction of switching activity at one or both inputs of the multipliers is a key to reduction of power consumption in FIR filters and equalizers. The switching activity can be reduced by use of transpose structure and by time-multiplexing of an unfolded filter. A well established retiming approach can be generalized to find those noncritical gates which can be operated with lower supply voltages to reduce the overall system power consumption. Index Terms--Commutators, digit-serial, dual supply voltage, FFT architecture, FIR filters, folding, hardware--software code-sign, low-power, Reed-Solomon coders, retiming, switching activity, unfolding, voltage scheduling.