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AlN thin films grown on different face sapphire substrates by metalorganic chemical vapor deposition were studied comprehensively by a variety of techniques including high resolution X-ray diffraction (HR-XRD), X-ray photoelectron spectroscopy (XPS), Raman scattering (RS) and theoretical calculations. Our results showed that substrate orientation has a drastic effect on the initial growth of AlN. The AlN films showed dominant semipolar (101) orientation but with slightly weaker individual features. Optical reflectance measurements confirmed that AlN films grown on different surface orientation sapphire substrates at the same time possessed different film thicknesses. It was found that the surface orientation also has a major influence on the dislocation density, crystallite size, and surface oxygen incorporation. Raman line width exhibited good correlation with XPS measurements. The combined analyses led to a better understanding of the variation in the quality of the AlN films grown on different faces of sapphires.

Comprehensive experimental and theoretical studies are reported to assess the vibrational and structural properties of 3C-SiC/Si (001) epilayers grown by chemical vapor deposition in a vertical reactor configuration. While the phonon features are evaluated using high resolution infrared reflectance (IRR) and Raman scattering spectroscopy (RSS) – the local inter-atomic structure is appraised by synchrotron radiation extended x-ray absorption fine structure (SR-EXAFS) method. Unlike others, our RSS results in the near backscattering geometry revealed markedly indistinctive longitudinal- and transverse-optical phonons in 3C-SiC epifilms of thickness d

This paper reports on the dependence of cycling or endurance in flash memory with the stress induced by low-pressure chemical vapor deposition (LPCVD) process. The deposited 12.5nm tetraethyl orthosilicate (TEOS) layer served as sacrificial oxide during source/drain (S/D) implantation, which was then subsequently removed. However, this deposited TEOS layer has been found to induce a stress on the channel which affects the flash memory cycling or endurance performance.

The synthesis of nano-crystalline Mg–Mn ferrites by a solution combustion method using citric acid and ammonia was investigated by varying the pH of the precursor solution, which played an important role in controlling the morphology of the synthesized powders. The phase formation, microstructure and electromagnetic properties were studied using X-ray diffraction, scanning electron microscopy, impedance analyzer and vibrating sample magnetometer. Single phase pure spinel Mg–Mn ferrite powders were obtained for all the samples at different pH (

Directing the morphological evolution of one-dimensional materials in order to tune their properties for a variety of practical applications in optical sensing and solar cells is an ongoing effort. Here, we establish a systematic method for exerting control over the morphology of nanowires (NWs) grown via a vapour–solid–solid (VSS) process from different metal catalysts. We use germanium, a technologically important material, to demonstrate how catalysts influence the axial growth rate of a crystalline core against the lateral vapour deposition of an amorphous shell which in turn deforms the NWs into straight, tapered or spiral geometries due to interfacial stress. Finite element method (FEM) and molecular dynamic (MD) simulations are further utilized to confirm the proposed mechanism of deformation in crystalline–amorphous core–shell NWs.

Magnesium silicates (MgxSiOy) and in particular forsterite (Mg2SiO4) owing to their low thermal expansion mismatch with metals are promising materials for bioactive coating of implants. Here, we report the electrophoretic deposition (EPD) of forsterite onto titanium substrates using different precursors. Unlike bulk samples which achieve full stoichiometry only beyond 1400 °C, non-stoichiometric magnesium silicate rapidly decomposes into magnesium oxide nanowires during sintering. Elemental mapping and X-ray diffraction suggest that oxygen diffusion followed by ion exchange near the substrate leads to formation of an interfacial Ti5Si3 layer. Pre-annealed forsterite powder on the other hand shows a comparatively lower diffusion rate. Overall, magnesium silicate coatings do not exhibit thermally induced microcracks upon sintering as opposed to calcium phosphate bioceramics which are currently in use.

Thermal oxides on the Ga-face of low defect density bulk gallium nitride (GaN) were controllably produced under varying conditions and subsequently analyzed. The thermal oxidation was performed in a dry oxygen atmosphere at different temperatures and different oxidation times. Each oxide layer was identified as the monoclinic β-Ga2O3 by a θ–2θ X-ray diffraction (XRD) scan. Complementary Auger electron spectroscopy (AES) and high-resolution X-ray photoelectron spectroscopy (XPS) were also performed to study the chemical and electronic states of the oxide. The surfaces of the as-grown oxide and the GaN surfaces (after oxide removal) were studied using scanning electron microscopy (SEM). The roughness of both surfaces was found to increase with increasing oxidation temperature. Schottky diodes were fabricated on the GaN surfaces after oxide removal to further examine the surface quality. An excess reverse leakage current was found for Schottky diodes fabricated on GaN surfaces that were oxidized at 950 °C or 1000 °C, indicating possible surface decomposition at these two temperatures. The characteristics of wet and dry etching of the gallium oxide layer were also investigated. Finally, metal–oxide–semiconductor (MOS) capacitors were fabricated using thermally oxidized bulk GaN substrates. Current–voltage (I–V) measurements showed a low reverse current of 1.5 pA at −10 V. The oxide breakdown field was determined to be 0.65 MV/cm. Capacitance–voltage (C–V) measurements displayed a deep depletion feature, and the interface trap density near the conduction band was estimated to be in the low 1011 eV−1 cm−2 range.

Vertical Schottky rectifiers have been fabricated on a free-standing n-GaN substrate. Circular Pt Schottky contacts with different diameters (50 μm, 150 μm and 300 μm) were prepared on the Ga-face and full backside ohmic contact was prepared on the N-face by using Ti/Al. The electron concentration of the substrate was as low as ∼7 × 1015 cm−3. Without epitaxial layer and edge termination scheme, the reverse breakdown voltages (VB) as high as 630 V and 600 V were achieved for 50 μm and 150 μm diameter rectifiers, respectively. For larger diameter (300 μm) rectifiers, VB dropped to 260 V. The forward turn-on voltage (VF) for the 50 μm diameter rectifiers was 1.2 V at the current density of 100 A/cm2, and the on-state resistance (Ron) was 2.2 mΩ cm2, producing a figure-of-merit (VB)2/Ron of 180 MW cm−2. At 10 V bias, forward currents of 0.5 A and 0.8 A were obtained for 150 μm and 300 μm diameter rectifiers, respectively. The devices exhibited an ultrafast reverse recovery characteristics, with the reverse recovery time shorter than 20 ns.

Silicon carbide (SiC) field-plate terminated Schottky diodes using silicon dioxide (SiO 2 ) dielectric experience high electric field in the insulator and premature dielectric breakdown, attributed to the lower dielectric constant of the oxide. To alleviate this problem we explore the use of high- k dielectrics, silicon nitride (Si 3 N 4 ) and sapphire (Al 2 O 3 ), on 4H-SiC by numerical simulations using Medici. The simulation results show significant improvement in blocking voltages by as much as 30% and much lower electric field within the dielectrics. There is also a slight reduction in the specific-on resistance ( R sp-on ) and a small increase in the forward current density due to the formation of an accumulation layer in SiC where the metal overlaps the dielectric. This effect is enhanced with increasing dielectric constant and decreasing dielectric thickness for a given dielectric.

A depletion mode metal–oxide–semiconductor field effect transistor (MOSFET) has been fabricated using 4H-SiC. The basic structure is the same as that of a conventional metal–semiconductor FET (MESFET), except that the Schottky barrier gate is replaced by a MOS gate that comprises a 50 nm silicon oxide (SiO2). The device has a pinch-off voltage of −1.0 V and a flat band voltage of 4.0 V. The drain current of the device can be substantially increased compared to the case of MESFET when a large positive gate voltage is applied, resulting in strong accumulation of electrons in the n-channel. Specifically, at a drain voltage of 25 V, the drain current is found to increase by 3.3 times when VGS is increased from 4.0 V (flat band condition) to 11.0 V (strong accumulation). Such gate bias condition, which is not possible in MESFETs, renders such devices ideal for high power applications. The electron mobility in the accumulation layer was found to be about 17.5 cm2/V s.

A double recessed SiC MESFET was proposed and its electrical performances were studied by numerical simulation. Our simulated results showed that the saturation current of the double recessed structure is about 77% larger than that of the conventional structure. However, their threshold voltages are comparable and are -9.2 and -8.4V for the double recessed and conventional structure, respectively. The output power density of the double recessed structure is about 37.5% larger than that of the conventional structure though its breakdown voltage is lower. The cut-off frequency (f"T) and the maximum oscillation frequency (f"m"a"x) of the double recessed structure are 15.3 and 70.6GHz, respectively, which are higher than that of the conventional structure. Therefore, the double recessed 4H-SiC MESFET has superior DC and RF performances compared to the similar device based on the conventional structure.

Reactive ion etching (RIE) of bulk 4H-SiC based on CHF"3-O"2 plasma was studied by varying the rf power and process pressure. The elements on the etched surface and the surface roughness were characterized by Auger electron spectroscopy and atomic force microscopy, respectively. It was found that the surface roughening is mainly caused by Al contamination and C rich layer (C residues) induced micromasking effect. The micromasking effect is in turn determined by the dc self-bias developed at the substrates. A threshold dc self-bias exists at around -320 to -330V, beyond which no micromasking effect was observed. This observation is explained in terms of physical ion bombardment and sputtering in the RIE process.

An improved analytical three-region model is proposed for short-channel SiC metal semiconductor field effect transistors (MESFETs). It takes into account two regions in the channel under the gate, and a third ungated high field region between the gate and the drain. This third region, which has been omitted in SiC MESFETs analytical models reported so far, experiences a large potential drop in short channel devices operating under high drain voltages. Therefore, its inclusion is critical in providing an accurate device modeling. To further improve our model, we have also incorporated parasitic resistances and incomplete ionization of dopants. Using this three-region analytical model, we have simulated the I-V characteristics of SiC MESFET with a [email protected] gate length, and obtained excellent agreement when compared with published experimental results.

A graphite mask was used to realize selective doping of aluminum/boron in 4H–SiC by thermal diffusion at a temperature range of 1800–2100 °C. The doping profiles investigated by secondary ion mass spectrometry show that a high aluminum concentration of 5×1019 cm−3 near the surface and linearly graded boron profile up to several micrometers in depth can be obtained. Hall effect measurement was also employed to obtain the electrical characteristics of the diffused region, from which the carrier concentration (1×1019 cm−3) and hole mobility (7 cm2/V s) at room temperature were extracted. Room temperature photoluminescence indicates that the dominant luminescence is attributed to the donor acceptor pair recombination, in which boron D complex is the prevailing center rather than Al and boron shallow acceptors. Cathodoluminescence micrographs clearly illustrate a pattern with the locally diffused regions. To confirm the viability of the diffusion process, planar p-n diodes with a fairly low forward voltage dro...

A process is described to enhance the diffusion rate of impurities in silicon carbide so that doping by thermal diffusion can be done at lower temperatures. This process involves depositing a thin film consisting of an oxide of the impurity followed by annealing in an oxidizing ambient. The process uses the lower formation energy of silicon dioxide relative to that of the impurity-oxide to create vacancies in silicon carbide and to promote dissociation of the impurity-oxide. The impurity atoms then diffuse from the thin film into the near-surface region of silicon carbide.

Tantalum pentoxide (Ta"2O"5) deposited by pulsed DC magnetron sputtering technique as the gate dielectric for 4H-SiC based metal-insulator-semiconductor (MIS) structure has been investigated. A rectifying current-voltage characteristic was observed, with the injection of current occurred when a positive DC bias was applied to the gate electrode with respect to the n type 4H-SiC substrate. This undesirable behavior is attributed to the relatively small band gap of Ta"2O"5 of around 4.3eV, resulting in a small band offset between the 4H-SiC and Ta"2O"5. To overcome this problem, a thin thermal silicon oxide layer was introduced between Ta"2O"5 and 4H-SiC. This has substantially reduced the leakage current through the MIS structure. Further improvement was obtained by annealing the Ta"2O"5 at 900^oC in oxygen. The annealing has also reduced the effective charge in the dielectric film, as deduced from high frequency C-V measurements of the Ta"2O"5/SiO"2/4H-SiC capacitors.

Results presented in this letter demonstrate that the effective channel mobility of lateral, inversion-mode 4H-SiC MOSFETs is increased significantly after passivation of SiC/SiO/sub 2/ interface states near the conduction band edge by high temperature anneals in nitric oxide. Hi-lo capacitance-voltage (C-V) and ac conductance measurements indicate that, at 0.1 eV below the conduction band edge, the interface trap density decreases from approximately 2/spl times/10/sup 13/ to 2/spl times/10/sup 12/ eV/sup -1/ cm/sup -2/ following anneals in nitric oxide at 1175/spl deg/C for 2 h. The effective channel mobility for MOSFETs fabricated with either wet or dry oxides increases by an order of magnitude to approximately 30-35 cm/sup 2//V-s following the passivation anneals.

Oxidation and silicidation have been found to enhance phosphorus diffusion and incorporation in 4H-SiC. Depth profiling by secondary ion mass spectrometry showed significant concentration of phosphorus in the order of 1018–1019 cm−3 in the near-surface region of 4H-SiC in both oxidation and silicidation-assisted phosphorus-diffused samples. However, silicidation was remarkably more effective than oxidation in promoting phosphorus diffusion, producing comparable phosphorus concentration at even greater depth at a temperature of only 900 °C. Specific contact resistance values of the phosphorus-doped samples confirmed feasibility of this method in ohmic contact fabrication on SiC.

The epitaxial growth of graphene on inexpensive, commercially available, free-standing polycrystalline 3 C-SiC has been achieved by solid state graphitization in ultrahigh vacuum. The structural and electronic properties of such epitaxial graphene (EG) have been explored by Raman spectroscopy, scanning tunneling microscopy (STM), and scanning tunneling spectroscopy (STS). The Raman results show that the grown EG is compressively stressed. The quality of such EG is similar to that on single-crystalline hexagonal SiC substrates. The STM measurements show that the EG grown on polycrystalline SiC presents atomically smooth surfaces across large regions of the underlying SiC substrate with some nanometer-scale features, such as one-dimensional (1-D) ridges, 1-D grain boundaries, and graphene in different stacking sequences. The STS measurements reveal the electronic properties of such EG at an atomic scale. Our approach suggests a more inexpensive way to grow high quality and large scale graphene and represent...

The authors present the fabrication and characterization of vertical-geometry Schottky-type ultraviolet (UV) photodetectors based on a bulk n-GaN substrate. By using low temperature rapid thermal annealing of the semitransparent Schottky contacts (nickel with 7% vanadium), they obtained an ultralow dark current of 0.56pA at −10V reverse bias. A responsivity of ∼0.09A∕W at zero bias was measured for wavelength shorter than the absorption edge of GaN, and it was found to be independent of the incident power in the range measured (50mW∕m2–2.2kW∕m2). The devices are visible blind, with an UV/visible contrast of over six orders of magnitude. An open-circuit voltage of 0.3V was also obtained under a broadband UV illumination.

The temperature-dependent electrical characteristics of Schottky rectifiers fabricated with a SiO2 field plate on a freestanding n− gallium nitride (GaN) substrate were reported in the temperature range of 298–473K. The Schottky barrier heights evaluated from forward current-voltage measurement revealed an increase of Schottky barrier height and series resistance but a decrease of ideality factor (n) with increasing temperature. However, the Schottky barrier heights evaluated from capacitance-voltage measurement remained almost the same throughout the temperature range measured. The Richardson constant extrapolated from ln(J0∕T2) vs 1∕T plot was found to be 0.029Acm−2K−2. A modified Richardson plot with ln(J0∕T2) vs 1∕nT showed better linearity, and the corresponding effective Richardson constant was 35Acm−2K−2. The device showed a high reverse breakdown voltage of 560V at room temperature. The negative temperature coefficients were found for reverse breakdown voltage, which is indicative of a defect-assi...

Postgrowth annealing was carried out to investigate the photoluminescence of zinc oxide (ZnO) nanorods synthesized using a thermal chemical vapor deposition method. The observed change in photoluminescence after the annealing processes strongly suggests that positively charged impurity ions or interstitial Zn ions are the recombination centers for green luminescence observed in the present sample. A model based on the interplay between the band bending at the surface and the migration of positively charged impurity ions or Zn ions was proposed, which satisfactorily explains the observed photoluminescence.

We report on the observation of ultraviolet lasing in optically pumped ZnO nanonails synthesized by thermal chemical vapor deposition method. The lasing threshold was found to be 17MWcm−2. Very sharp emission peaks (full width at half maximum of 0.08nm) were observed in the emission spectrum, indicating a high Q factor of the cavity formed by the hexagonally shaped nanonail head. The analysis of the lasing spectra strongly suggests the whispering gallery mode lasing from a hexagonally shaped head of the single ZnO nanonail.

A vertical Schottky diode rectifier was fabricated using a bulk n−GaN wafer. Pt Schottky contacts were prepared on the Ga face and full backside ohmic contact was prepared on the N face by using Ti∕Al. The root mean square surface roughnesses of the Ga and N faces are 0.61 and 4.7nm, respectively. A relatively high breakdown field of 5.46kV∕cm was achieved with no additional edge termination. The breakdown field decreases as the size of the device increases. The background electron concentration of the bulk GaN wafer was low (5×1015cm−3), which may lead to a relatively high breakdown field even with no special edge termination. The forward turn-on voltage was as low as 2.4V at the current density of 100A∕cm2. The device exhibited an ultrafast reverse recovery characteristics (reverse recovery time

Photoinduced transient spectroscopy (PITS) and photoluminescence spectroscopy measurements were carried out on samples of liquid‐encapsulated Czochralski‐grown semi‐insulating GaAs which have been diffused with copper at 550 °C. The PITS curves, taken at different depths from the surface, confirm that the copper‐related acceptor level at 0.51 eV is due to a complex, which we assign to CuGaVAs. The PITS results show that an acceptor level at 0.51 eV in GaAs, previously assigned to iron impurity, can also be caused by copper. Photoluminescence studies show that the emission peak at 1.36 eV, commonly attributed to CuGa, also varies with depth. This variation is explained by the predominance of copper in the form Cu+i near the copper‐covered surface. We have shown, from both PITS and photoluminesence results, the significance of the capping effect of a copper film during annealing, and this effect must be taken into account in the analysis of copper diffusion data in GaAs.

A cheap but versatile microcomputer-controlled temperature controller costing less than $100 is described. The system is built around a Timex/Sinclair 1000/ZX81 microcomputer. This is a truly digital system employing the proportional-integral-derivative feedback-control algorithm, thus making the system capable of producing any required temperature profile at a low cost.

Photoinduced transient spectroscopy (PITS) studies of samples of copper contaminated annealed semi‐insulating GaAs in the temperature range of 274–384 K show two dominant levels at about Ev +0.5 eV and about Ec −0.59 eV in addition to the EL2 levels at about Ec −0.80 eV. Depth profiling using chemical etching followed by PITS measurements shows a competing process between the defects responsible for the level at Ev +0.5 eV and that at Ec −0.59 eV. The former is predominantly found near the surface and the latter is dominant in the interior. From the depth profiling results, we have determined that the diffusion constants for these two types of defects are about 4.7×10−10 cm2 s−1 and 5.2×10−10 cm2 s−1, respectively. We propose that the level at Ev +0.50 eV is due to a copper related complex and the level at Ec −0.59 eV is due to native defects. The copper related level at about Ev +0.50 eV is different from the often seen copper related defect level at around Ev +0.40 eV. The presence of these two levels w...

The presence of deep levels in several samples of InP metal‐insulator‐semiconductor (MIS) structures was studied using the deep level transient spectroscopy technique. The InP MIS structures were fabricated using three different methods of oxide formation, two of which are chemical oxides and the third is plasma‐grown oxide. Defect levels ranging from (Ec−0.22) to (Ec−0.6) eV were observed in the samples. However, the levels at about (Ec−0.22) and (Ec−0.35) eV were detected only after increasing the reverse‐bias voltage to −2 V at a temperature of about 390 K. This phenomenon occurred in all the samples studied, irrespective of the method of oxidation. The appearance of the peaks corresponding to the shallower traps is irreversible and may explain the performance instability commonly encountered in InP MIS‐based devices.