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This article presents a novel two‐element printed monopole MIMO design for dual‐band operation with high port isolation and compact size. Upper‐band (f2) decoupling is achieved by the optimal meandering of the monopole, while the lower band (f1) decoupling is attained by the insertion of a new T‐shaped neutralization line structure. Unlike conventional decoupling techniques, the proposed method offers independent control of decoupling performance at two widely spaced frequency bands, without any bulky structure. For validation, a printed monopole MIMO antenna designed to operate at 2.45 and 5.0 GHz, is fabricated and measured. Simulation and experimental results indicate that the proposed dual‐band antenna exhibit high port isolation (20 dB/25 dB) with enhanced efficiency (92%) and reduced ECC values (<0.05). [ABSTRACT FROM AUTHOR]

This brief presents a new design methodology of single-chip reconfigurable CMOS RF power amplifier (PA) supporting both dual-band and multi-power-mode operation. The proposed architecture utilizes a novel switched-capacitor based output network to facilitate differential signal combining and impedance transformation at two widely separated frequency bands. It can offer three distinct output power levels (saturation) to be selected for multi-power-mode applications. Besides, closed-form explicit equations are readily available for the evaluation of component values. For verification, a PA operating at 1.8/2.6 GHz (non-concurrent), with three distinct saturation power levels (21, 23, 26 dBm) and peak efficiency of about 30%, is designed and fabricated using $0.35~{\mu }\text{m}$ CMOS process. [ABSTRACT FROM AUTHOR]

A novel wideband decoupling technique for multiple-input–multiple-output (MIMO) antenna arrays is proposed. Broadband isolation is achieved by creating controllable transmission zeros (S21 = 0) at two separated frequencies. The newly developed decoupling network is compact in size due to the elimination of multiple transmission line elements and the external matching circuit. Simulation and measurement results show that the proposed method can offer substantial enhancement in port isolation, pattern diversity (envelope correlation coefficient), and radiation efficiency over the designated frequency range. [ABSTRACT FROM AUTHOR]

This letter presents a modified Doherty power amplifier (DPA) combining network with wide bandwidth (BW) and high power utilization factor (PUF). For the first time, the impact of the excessive phase dispersion of matching networks on the performance of conventional broadband DPA is analytically revealed. For dispersion compensation, an optimized adaptive combining load is introduced to enhance the achievable DPA BW and PUF. For verification, a 42-dBm equal-cell DPA is prototyped to cover 1.4–2.55 GHz. Measurement results indicate that, over the prescribed frequency range, a PUF of over 0.95, back-off efficiency (6 dB) of 48%–58%, and saturation efficiency of 62%–74% can be achieved. Moreover, under WCDMA excitation, the adjacent channel leakage ratio (ACLR) was found to be better than −32 dBc with average efficiency of over 45% without applying digital predistortion techniques. [ABSTRACT FROM AUTHOR]

In this paper, a mixed topology for high efficiency, broadband Doherty power amplifier (DPA) is proposed. The transistor gate biases are set to deep Class-AB for the carrier device and deep Class-C for the peaking device, which enable the DPA to achieve its high efficiency. However, this biasing scheme leads to an inadequate back-off range, which in the past limited applicability. To compensate for this reduced back-off range, a “ $\pi $ -type” harmonic injection network (HIN) is integrated into the DPA thereby allowing the second harmonic to be injected between the two active devices. This achieves waveform engineering, which enhances the output power of the peaking amplifier. However, the use of this HIN leads to a reduction in bandwidth due to a mismatch at the fundamental frequency. A bandwidth compensation technique is then proposed, thereby reducing the peaking device drain impedance variation. This mitigates the reduction in bandwidth as a result of the HIN. A high-efficiency DPA is prototyped based on two identical 10-W gallium nitride HEMTs. Measurement results show that a drain efficiency of greater than 60% is achieved at 5.3–6-dB output back-off power from 1.4 to 2.1 GHz. [ABSTRACT FROM AUTHOR]

In this paper, a novel modified Doherty power amplifier (DPA) that allows for extended output back-off (OBO) range, improved power utilization factor (PUF), and increased peak power over a broad bandwidth is proposed. It starts with an in-depth analysis of the modified DPA circuitry that first revealed the ability to control the impedances seen by the main transistor versus frequency by properly setting the magnitude and phase of the ratio between the peaks of the combining currents. This is then exploited to maximize the peak power and enhance the achievable bandwidth. Furthermore, a complex-to-real output matching network is incorporated in the auxiliary path and its parameters are carefully chosen to produce proper load modulation while satisfying the required peak combining current ratio. For validation purpose, a DPA prototype is designed to operate over the frequency range of 1.35–2.05 GHz with an OBO of 9 dB. Under the continuous-wave excitation, the DPA prototype maintained the drain efficiency (DE) of 52%–55% and 65%–75% at 9-dB OBO and peak power, respectively, over the entire targeted band. In addition, the measured peak power and PUF were about 42 dBm and higher than 0.9, respectively. The linearizability of the DPA prototype using digital predistortion (DPD) with memory was assessed while being driven with a 40-MHz carrier-aggregated signal with a peak-to-average power ratio of 8.9 dB and at an average output power of 33 dBm. When the carrier frequency is swept over the entire band, the measurement revealed an adjacent channel leakage ratio of better than −46.5 dBc after DPD with an average DE of 49.3%–53%. [ABSTRACT FROM AUTHOR]

A novel dual-band decoupling and matching technique for asymmetric two-element antenna arrays is proposed. Decoupling and matching at two widely separated frequencies is accomplished by using a two-layer (level) network approach. Unlike previous works, analytical solution is readily available and prematching of the radiating elements is no longer required. Simulation and experimental results show that the proposed method can offer improved port isolation and input return loss, enhanced efficiency, and increased radiation pattern diversity in both frequency bands. [ABSTRACT FROM PUBLISHER]

This letter presents, for the first time, the design of a novel antenna with continuous control of polarization states. Polarization agility is attained by the adoption of a dual-polarized antenna and a newly developed signal control device (using varactor diodes only). The proposed circuit also features simple control circuitry, potentially wideband, almost zero dc power consumption, and is amendable to antenna array realization. For experimental demonstration, the measured results of a 1.8-GHz antenna implemented on microstrip are shown. [ABSTRACT FROM PUBLISHER]

This letter starts with describing the efficiency of two-way Doherty power amplifier (DPA) in the presence of the nonlinear phase distortion of the constituent transistors. Combined with the proper choice of the complex-valued load impedance’s reactance, this analysis directed the design of DPA with enhanced efficiency over extended output back-off power region and bandwidth. Results of measurement conducted using a proof-of-concept demonstrator designed to operate in the frequency band ranging from 1.35 to 1.7 GHz revealed average efficiency of 59%–62% under 20-MHz long-term evolution modulated signal. [ABSTRACT FROM PUBLISHER]

This paper presents, for the first time, the linearity study of a varactor-based microwave attenuator. In particular, a novel technique is proposed to linearize the attenuator in terms of both main-tone and intermodulation distortion (IMD) performance. The enhancement circuit is simple to implement and can offer a reduction of the IMD level of over 20 dB. Linearization is achieved by shifting the biasing point of the tuning diodes (under large attenuation operation) away from the highly nonlinear region. For verification, both simulated and measured results of a 1-GHz variable attenuator with and without linearization are given. [ABSTRACT FROM PUBLISHER]

In this paper, a novel Doherty power amplifier (DPA) configuration with an auxiliary transformer is proposed for broadband operation. Theoretical analysis reveals that the proposed design can offer enhanced power utilization factor (PUF) and wideband Doherty behavior. The optimal design of the auxiliary transformer is identified with an aim to provide good impedance matching and minimal group delay. Based on the proposed theory, a 1.6–2.4-GHz 20-W DPA with improved PUF is designed, simulated, and measured. Under continuous wave excitation, measurement results indicate that the proposed DPA can achieve a PUF of 0.9, good Doherty behavior over the entire frequency band with a 6-dB back-off efficiency of 55%–64%, and saturated efficiency of 68%–76%. In addition, by the use of single-carrier WCDMA signal (centered at 2 GHz) with peak-to-average power ratio of 6.6 dB and at an average output power of 37 dBm, an average drain efficiency of 56% is obtained with adjacent channel leakage power ratio of better than -37 dBc. [ABSTRACT FROM PUBLISHER]

This letter presents, for the first time, the design of a reconfigurable rat-race coupler with dual-band operation. This device can offer power-dividing ratio of K^2 or $\infty $ at two different frequency bands. The proposed design also features low insertion loss, high port isolation, compact size, single control voltage, and minimal number of RF switches. For demonstration, both simulation and measured results of a 0.9-/2-GHz reconfigurable rat-race coupler implemented on microstrip are given. [ABSTRACT FROM PUBLISHER]

This letter presents the design of a symmetrical Doherty power amplifier (DPA) with extended high-efficiency range by using a new and explicit circuit model. Theoretical analysis reveals that by the adjustment of the electrical length of transmission line sections in the proposed circuit model, new DPA variants with simple circuitry and enhanced output back-off (OBO) are obtained. For experimental verification, a 42-dBm, 2-GHz DPA with OBO of 9.5 dB was designed and fabricated using identical GaN HEMT devices. Under continuous-wave stimulation, measurement results indicate good Doherty behavior can be obtained with 9.5-dB back-off efficiency of 51%–61% and saturation efficiency of 68%–72% over 1.85–2.1 GHz. Moreover, with single carrier WCDMA signal (centered at 2.1 GHz) and peak-to-average power ratio of 9.6 dB, the proposed design is found to deliver an average drain efficiency of 58% and adjacent channel leakage power of −47 dBc at an output power level of 32.5 dBm. [ABSTRACT FROM PUBLISHER]

In this paper, a novel Doherty power amplifier (DPA) configuration with a complex combining load (CCL) is presented to extend the high-efficiency range of the amplifier. Theoretical analysis of dynamic load span, current ratio, and drain efficiency reveals that CCL can offer a new degree of freedom to boost the output back-off (OBO) of the DPA. For verification, a 2-GHz equal-cell GaN HEMT-based DPA is simulated, prototyped, and measured with both complex and resistive combining loads (RCLs). Under continuous wave (CW) excitation, measurement results show that the proposed DPA can attain an OBO of 9.1 dB, which is 3.6 dB higher than that of the RCL design. In addition, by the use of single-carrier WCDMA signal with peak-to-average power ratio of 9.6 dB and at an average output power of 33.2 dBm, the proposed design is found to deliver an average drain efficiency of 57.4%. In the absence of multi-cell or enlarged auxiliary device, this approach offers a low-cost and simple DPA solution with extended OBO, as well as good Doherty behavior. [ABSTRACT FROM AUTHOR]

This paper presents, for the first time, the theoretical and experimental study of broadband rat-race coupler design with a tunable power dividing ratio. Wide fractional bandwidth (around 40%) is accomplished by the adoption of frequency compensating networks with specific derivatives of even- and odd-mode admittances. General formulation is analytically carried out to lay down the design principles of these networks. The proposed design also features wide tuning range (almost 20 dB), low insertion loss, high port isolation (over 25 dB), good return loss, simple structure, compact size, zero dc power consumption, and single voltage operation with a minimal number of tuning diodes. For demonstration, both simulated and measured results of a 1-GHz tunable rat-race coupler implemented on microstrip are shown. [ABSTRACT FROM PUBLISHER]

This paper presents the design of a low-voltage current-reused single-sideband mixer (SSBM) and quadrature voltage-controlled oscillator (QVCO) for Mode-1 multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer application. The proposed architecture is a low-voltage and low-power solution by stacking the SSBM on top of a pMOS parallel QVCO. For low-voltage operation, two symmetric transformers are used to perform quadrature oscillation and signal coupling. In addition, source degeneration capacitors are introduced to eliminate bimodal oscillation in QVCO and fix the phase sequence of the quadrature signal. For experimental demonstration, the proposed circuit was fabricated in a 0.18-\mu\ m CMOS technology. The prototype occupies a core area of 0.8 \ \ mm^2 and consumes about 11 mA from a 1.6-V power supply. Measurement results show that the image spurious rejection is over 43 dBc and the output phase noise of the SSBM is better than -\111.4 dBc/Hz at 1-MHz offset from carrier (3.432 GHz). [ABSTRACT FROM PUBLISHER]

This paper presents, for the first time, a novel rat-race coupler design with tunable power dividing ratio. Wide tuning ratio is accomplished by the use of two tuning diodes and a single control voltage. Ideal port isolation and return loss characteristics, evaluated at the center frequency of operation, are proven for all dividing ratios. The structure is simple to construct and involves 50-ohm lines only. For verification, the simulated and measured results of a 1-GHz rat-race coupler implemented on microstrip are shown. [ABSTRACT FROM AUTHOR]

This paper presents, for the first time, the novel design of a dual-band crossover. The proposed circuit features planar implementation with moderate line impedance, compact layout, and widely separated frequency bands. Moreover, simple and explicit closed-form expressions are available for the exact evaluation of the line impedances. For verification, both simulated and measured results of a microstrip crossover operating at 800 MHz and 1.2 GHz are given. [ABSTRACT FROM AUTHOR]

This paper presents a novel design of a microwave power divider with enhanced spurious suppression. The proposed circuit features simple implementation with moderate line impedance, flexible layout design, and extended stopband bandwidth with three controllable transmission zeros. Moreover, explicit closed-form expressions are available for the evaluation of circuit parameters. For verification, the simulated and measured results of a 1-GHz power divider implemented on microstrip are shown. [ABSTRACT FROM AUTHOR]

This paper presents the design of a novel power-divider circuit with an unequal power-dividing ratio. Unlike the conventional approaches, the characteristic impedance values of all the branch lines involved are independent of the dividing ratio. The electrical lengths of the line sections are the only circuit parameters to be adjusted. Moreover, the proposed structure does not require impedance transformers at the two output ports. By the introduction of a transmission line between one of the output ports and the isolation resistor, a flexible layout design with reduced parasitic coupling is achieved. For verification, the measured results of a 2: 1 and a 4: 1 power-divider circuits operating at 1 GHz are given. A relative bandwidth of over 20% is obtained based on a return loss and port isolation requirement of -20 dB. [ABSTRACT FROM AUTHOR]

This paper presents the design of a new, Wilkinson power divider for dual-band application. The proposed circuit also features a simple structure with realistic impedance values, distributed design with reduced parasitic effect (in compared to lumped component), and exact solution (ideal characteristics). Closed-form design equations are derived using the even- and odd-mode formulation. For verification, the measured results of a microstrip power divider operating at 1 and 2 GHz is shown. [ABSTRACT FROM AUTHOR]

This paper presents a novel and simple linearization scheme for a CMOS double-balanced mixer based on the use of multibias dual-gate transistors. In this technique, intermodulation-distortion (IMD) components with proper phase relationship, generated by devices operating at different bias conditions, are combined together to improve the linearity of mixers. For experimental verification, the measured performance of a fabricated CMOS mixer is shown. Over 35 dB of IMD reduction is achieved by the proposed method under proper biasing condition. [ABSTRACT FROM AUTHOR]

Investigates the multistage amplifier linearization based on the generalized low-frequency signal-injection technique. Block diagram of the amplifying system; Intermodulation distortion components; Effects of gain error.

Presents a linearization scheme for radio frequency amplifiers based on simultaneous harmonic and baseband signal injection. Incorporation of second-order frequency components into the input of the main amplifier; Presentation of the analytical formulation of baseband, harmonic and the proposed injection techniques; Limitation of the proposed method.

Proposes a compact two-dimensional full-wave finite-difference frequency-domain method for general guided wave structures. Analysis of the dispersion characteristics of a general guided wave structure; Elimination of the longitudinal field components in the proposed method; Number of transverse field components in the resulting eigen equation.

Examines the dependency of in-band noise performance upon circuit and device parameters of microwave filters. Derivation of a general expression for the active filter noise figure evaluation; Factors affecting the optimization of the overall noise figure; Impact of linearity on noise performance.

Presents the derivation of the relationship between oscillator output power and various circuit and device parameters. Hindrances to the achievement of high output power in metal semiconductor field-effect transistor oscillators; Determination of optimum operating conditions for maximum oscillator efficiency; Use of an oscillator open-loop model.

Examines the dependency of the third-order intermodulation distortion and power saturation upon circuit and device parameters of an active bandpass filter using negative-resistance compensation. Performance of a nonlinear analysis by means of the Volterra series formulation; Measured performances of some 900-MHz experimental MESFET bandpass filters.

Presents a computer-aided design-oriented analytical formula for the determination of the characteristic parameters of asymmetrical coupled lines of a conductor-backed coplanar type waveguide. Method of analysis and dimensional parameters; Self and mutual capacitance values evaluated by the proposed method and a spectral-domain approach.

This letter presents, for the first time, the theoretical and experimental investigation of the group delay characteristics of a rat-race coupler with variable power dividing ratio. By analytically study, the group delays associated with different transmission paths are found to be identical and can be made independent of the power dividing ratio by the proper design of the embedded networks. For validation, both simulated and measured results of a 1 GHz variable rat-race coupler implemented on microstrip are shown. [ABSTRACT FROM PUBLISHER]

A novel, current reused, voltage-controlled oscillator (VCO) and injection-locked frequency divider (ILFD) with variable dividing ratio is presented and implemented in UMC 0.18 \mum triple-well CMOS process. The proposed architecture allows compact and low power solution to be attained by the stacking of a ring-type ILFD and a transformer based VCO. The LC VCO provides the wideband differential output and the two-stage ring oscillator generates the quadrature output with selectable division ratios. Experimental results show an output frequency range from 0.58 to 3.11 GHz and a phase noise level of - 112.5~dBc/Hz at 1 MHz offset from carrier (5.72 GHz). This chip occupies a core area of 0.5\,\times\,0.3 mm^2 and consumes 4.7 mA from a 1.8 V power supply. [ABSTRACT FROM PUBLISHER]

A low-voltage, current-reused, quadrature voltage controlled oscillator (QVCO) and divide-by-4 frequency divider (FD4) architecture is presented for the first time. The proposed architecture features compact and low voltage operation by the proper stacking of a ring-type injection locked FD4 and a back-gate coupled QVCO. This design lowers the power consumption and eliminates the need of high frequency divider as well as buffering stage. The circuit has been implemented in 0.18-\mum triple-well CMOS process. Experimental results show a phase noise level of -114.1 dBc/Hz at 1 MHz offset from carrier (2.2 GHz). This chip occupies a core area of 0.9\times 0.35\ mm^2 and consumes 2.7 mA from a 1.3 V power supply. [ABSTRACT FROM PUBLISHER]

This letter presents, for the first time, a novel design of unequal power divider with dual-harmonic rejection. Explicit closed-form design formulas are made available for circuit parameter extraction. The proposed circuit features simple construction and wide spurious suppression bandwidth. For demonstration, the simulated and experimental results of a 1 GHz, 2:1 power divider implemented on microstrip are given. [ABSTRACT FROM PUBLISHER]

A 2.4 GHz quadrature-input programmable frequency divider with step size of 0.5 is demonstrated in a standard 0.35 \mum CMOS process. Fractional division is realized by phase switching between the cross-coupled divide-by-4 injection-locked frequency divider outputs. The proposed circuit exhibits an operation frequency range from 2.24 to 2.70 GHz and consumes less than 5.13 mW with a 1.5 V supply. [ABSTRACT FROM PUBLISHER]