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This paper proposed a fabrication of p-type Germanium (Ge) tri-gate field-effect transistors (Tri-gate FETs) via green nanosecond laser crystallization (GNSLC) and counter doping (CD). By using the GNSLC, the nano-crystalline-Ge (nc-Ge) with a grain size of 80 nm could be turned into polycrystalline Ge (poly-Ge) with that of above $1 ~\mu \text{m}$ . With the increase of laser power, the improved crystallinity and lower hole concentration of poly-Ge were also verified by Raman spectra and Hall measurement. To fabricate the high-performance Ge Tri-gate FETs, the chemical-mechanical planarization (CMP) and counter doping (CD) process would further be utilized. The CMP process eliminated the surface roughness of poly-Ge while the CD process decreased the hole concentration of poly-Ge or even converted that into an N-type one. The effect of the CD on the performance of p-type Ge Tri-gate FETs was further investigated. Consequently, the GNSLC Ge Tri-gate FETs showed threshold voltage (Vth) of −0.41 V, ION of $7.10\times 10\; ^{-6}$ , and IOFF of $1.28\times 10\; ^{-9}$ respectively, indicating better crystallinity of the Ge channel.

The stress of TSV with different dimensions under annealing condition has been investigated. Since the application of TSV and bonding technology has demonstrated a promising approach for vertical connection in HBM stacking, the stress caused by Cu TSV substrates needs to be carefully investigated. The changing in TSV size under the same TSV aspect ratio does not obviously affect the stress toward the surroundings. On the other hand, the adjustment on TSV aspect ratios results in different stress values, and the aspect ratio of 1:8 results in the largest stress in the analysis. Besides, the annealing temperature has more influence on the stress than the size of TSV. As a consequence, reduction on the annealing temperature is an effective method to achieve a low stress for TSV in HBM stacks. Therefore, several methods for low temperature hybrid bonding have also been reviewed and discussed.