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To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.sysarc.2007.01.006 Byline: Stamatis Vassiliadis, Ioannis Sourdis Keywords: Interconnection networks; Multiprocessor parallel systems Abstract: In this paper, we introduce the FLUX interconnection networks, a scheme where the interconnections of a parallel system are established on demand before or during program execution. We present a programming paradigm which can be utilized to make the proposed solution feasible. We perform several experiments to show the viability of our approach and the potential performance gain of using the most suitable network configuration for a given parallel program. We experiment on several case studies, evaluate different algorithms, developed for meshes or trees, and map them on "grid"-like or reconfigurable physical interconnection networks. Our results clearly show that, based on the underlying network, different mappings are suitable for different algorithms. Even for a single algorithm different mappings are more appropriate, when the processing data size, the number of utilized nodes or the hardware cost of the processing elements changes. The implication of the above is that changing interconnection topologies/mappings (dynamically) on demand depending on the program needs can be beneficial. Author Affiliation: Computer Engineering, TU Delft, The Netherlands Article History: Received 31 December 2006; Accepted 17 January 2007 Article Note: (footnote) [star] This work was supported by the European Commission in the context of the Scalable computer ARChitectures (SARC) integrated project #27648 (FP6). This paper is an extended version of .

An associative approach involving the mapping of algorithms onto a set of bit-patterns, matched in parallel, provides flexibility and quick execution for implicit routing algorithms. The mapping of a large number of routing algorithms for a broad range of interconnection network topologies indicates that the number of required bit-patterns and the topology degree are of the same order. The hardware requirement for the scheme is low. Three cases showing the capabilities of the router approach are discussed.

The present paper describes a question answering system based on fuzzy logic. The proposed system provides the capability to assess whether a database contains information pertinent to a subject of interest by evaluating each comment in the database via a fuzzy evaluator that attributes a fuzzy membership value indicating its relationship to such subject. An assessment is provided for the database as a whole regarding its pertinence to the subject of interest, and consequently comments that are considered irrelevant to the subject may be discarded. The system has been developed for the examination of databases that were created during the development of the IBM 4381 computer systems, for bookkeeping purposes, to assess whether such databases contain information pertinent to the functional changes that occurred during the development cycle. The system, however, can be applied with minimal changes to a variety of circumstances, provided that the fundamental assumptions for the development of the membership functions are respected in the new application. Its applicability, without modifications, assuming the same subject of interest, is granted for databases comprising similar characteristics to that of the original database for which the system has been developed. Index Terms - Approximate reasoning, fuzzy reasoning, fuzzy logic, fuzzy sets, fuzzy systems, fuzzy measure, membership functions, question answering system, and database evaluation

Piece-wise first- and second-order approximations are employed to design commonly used elementary function generators for neural-network emulators. Three novel schemes are proposed for the first-order approximations. The first scheme requires one multiplication, one addition, and a 28-byte lookup table. The second scheme requires one addition, a 14-byte lookup table, and no multiplication. The third scheme needs a 14-byte lookup table, no multiplication, and no addition. A second-order approximation approach provides better function precision; it requires more hardware and involves the computation of one multiplication and two additions and access to a 28-byte lookup table. We consider bit serial implementations of the schemes to reduce the hardware cost. The maximum delay for the four schemes ranges from 24-to 32-bit serial machine cycles; the second-order approximation approach has the largest delay. The proposed approach can be applied to compute other elementary function with proper considerations. Index Terms--Elementary function generators, hardwired neuroemulators, neural-network functions, piecewise approximation, square root implementation, trigonometric functions.

This paper investigates threshold based neural networks for periodic symmetric Boolean functions and some related operations. It is shown that any n-input variable periodic symmetric Boolean function can be implemented with a feedforward linear threshold-based neural network with size of O(log n) and depth also of O(log n), both measured in terms of neurons. The maximum weight and fan-in values are in the order of O(n). Under the same assumptions on weight and fan-in values, an asymptotic bound of O(log n) for both size and depth of the network is also derived for symmetric Boolean functions that can be decomposed into a constant number of periodic symmetric Boolean subfunctions. Based on this results neural networks for serial binary addition and multiplication of n-bit operands are also proposed. It is shown that the serial addition can be computed with polynomially bounded weights and a maximum fan-in in the order of O(log n) in O(n/log n) serial cycles, where a serial cycle comprises a neural gate and a latch. The implementation cost is in the order of O(log n), in terms of neural gates, and in the order of O([log.sup.2] n), in terms of latches. Finally, it is shown that the serial multiplication can be computed in O(n) serial cycles with O(log n) size neural gate network, and with O(n log n) latches. The maximum weight value in the network is in the order of O([n.sup.2]) and the maximum fan-in is in the order of O(n log n). Index Terms - Counters, feedforward neural networks, majority logic gates, McCulloch-Pitts neural networks, parity, serial binary adders, serial binary multipliers, symmetric functions, threshold logic.

Proposes a scheme to reduce the size for small depth feed-forward linear networks performing binary addition and related functions with threshold logic. Advantages of the proposed scheme over other schemes in terms of size, fan-in requirements and weight measurements.

Addresses the issues related to the definition for failures, faults, and errors and their separability as it pertains to computing systems. Information on historical databases; Description of the methodology that can be used to analyze the database and obtain the pertinent information; Evaluation of the historical data collected.

This paper proposes a novel digital neural network architecture referred to as the Sequential PIpelined Neuroemulator or Neurocomputer (SPIN). The SPIN processor emulates neural networks producing high performance with minimum hardware by sequentially processing each neuron in the modeled completely connected network with a pipelined physical neuron structure. In addition to describing SPIN, performance equations are estimated for the ring systolic, the recurrent systolic array, and the neuromimetic neurocomputer architectures, three previously reported schemes for the emulation of neural networks, and a comparison with the SPIN architecture is reported. [ABSTRACT FROM AUTHOR]

Semantic networks as a means for knowledge representation and manipulation are used in many artificial intelligence applications. A number of computer architectures, that have been reported for semantic network processing, are presented in this paper. A novel set of evaluation criteria for such semantic network architectures has been developed. Semantic network processing as well as architectural issues are considered in such evaluation criteria. A study of how the reported architectures meet the requirements of each criterion is presented. This set of evaluation criteria is useful for future designs of machines for semantic networks because of its comprehensive range of issues on semantic networks and architectures. [ABSTRACT FROM AUTHOR]