1. EJ-FAT Joint ESnet JLab FPGA Accelerated Transport Load Balancer
- Author
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Stacey Sheldon, Yatish Kumar, Michael Goodrich, and Graham Heyes
- Subjects
Computer Science - Networking and Internet Architecture ,Networking and Internet Architecture (cs.NI) ,FOS: Computer and information sciences - Abstract
To increase the science rate for high data rates/volumes, Thomas Jefferson National Accelerator Facility (JLab) has partnered with Energy Sciences Network (ESnet) to define an edge to data center traffic shaping / steering transport capability featuring data event-aware network shaping and forwarding. The keystone of this ESnet JLab FPGA Accelerated Transport (EJFAT) is the joint development of a dynamic compute work Load Balancer (LB) of UDP streamed data. The LB is a suite consisting of a Field Programmable Gate Array (FPGA) executing the dynamically configurable, low fixed latency LB data plane featuring real-time packet redirection at high throughput, and a control plane running on the FPGA host computer that monitors network and compute farm telemetry in order to make dynamic decisions for destination compute host redirection / load balancing., Comment: Published at INDIS workshop at Supercomm 2022
- Published
- 2023
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