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4. Factors affecting an efficient sealing of porous low-k dielectrics by physical vapor deposition Ta(N) thin films

Author

Iacopi, F., Tökei, Z., Le, Q. T., Shamiryan, D., Conard, T., Brijs, B., Kreissig, U., Hove, M., Maex, K., Iacopi, F., Tökei, Z., Le, Q. T., Shamiryan, D., Conard, T., Brijs, B., Kreissig, U., Hove, M., and Maex, K.

Abstract

The deposition of homogeneous thin films on porous substrates has been investigated. The thin film deposition of Ta(N) by physical vapor deposition on porous films with different average pore sizes and material compositions has been studied. The continuity of Ta(N) films on top of porous low-k dielectrics is evaluated by means of ellipsometric porosimetry combined with sheet resistance and atomic force microscopy measurements. Interface reactions are analyzed by x-ray photoelectron spectroscopy profiling. It has been observed that the minimal Ta(N) thickness required to obtain a continuous metal layer on top of the porous film depends, on the one hand, on the porosity and pore size and, on the other hand, on the chemical interaction of the thin film with the porous substrate. The sealing of pores is favored by the presence of carbon in the dielectric matrix. This is explained through a mechanism of local enhancement of the degree of crosslinking in the dielectric matrix, catalyzed by Ta.

Published
2002

6. Alternative gate dielectric materials

Author

Sven Van Elshocht, An Hardy, S. De Gendt, Christophe Adelmann, David P. Brunco, Matty R. Caymax, Thierry Conard, Pietro Delugas, Peer Lehnen, Denis Shamiryan, Rita Vos, Thomas Witters, Paul Zimmerman, Marc M. Meuris, Marc M. Heyns, Van Elshocht, S., HARDY, An, De Gendt, S., Adelmann, D., Brunco, D., Caymax, M., Conard, T., Delugas, P., Lehnen, P., Shamiryan, D., Vos, R., Witters, P., Zimmerman, P., MEURIS, Marc, and Heyns, M.

Abstract

The semiconductor industry is facing the challenging task of finding a candidate to replace silicon oxide, which has been the CMOS gate dielectric of choice for more than 50 years. A material with a dielectric constant (k) higher than SiO2 will allow making the dielectric thicker by a factor of k/k(SiO2), hence lowering the gate current leakage levels, and this without reduction of the capacitance and thus performance.

Published
2006

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